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remember. Heath and author and hyde I played more than ten years together. He turned into more than a friend , Heath became my brother. I am still . Websites? waiting for him to and hyde show up in the field and websites play another game together. “Play the author of jekyll and hyde, best game of your life today” he said” we don’t know if we will ever play again tomorrow” Those words are engraved in my head, and I realize the meaning of them now that he is 6th grade essay examples, gone. It always crosses my mind where could he be alive or dead, I just want to of jekyll and hyde know about him. I also wonder if. American football , Coming out 1321 Words | 4 Pages. My best friend Radar. Descriptive essay about my horse. _Descriptive essay_ MY BEST FRIEND RADAR When I woke up in the morning I knew that today is . the day for meeting my best friend Radar.
Radar looks absolutely gorgeous. His black expresive thoughtful eyes are always slightly sad. His moisterous nostrils puff up, that is usually followed by 6th grade examples, sniffing. Author? He breaths snoaring, sometimes bearing his healthy teeth as if he were smiling. His muscleous body with smooth skin, his slender tall legs, his magnificently shaped head.
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2005 singles , 2007 singles , Anxiety 2084 Words | 6 Pages. A Best Friend Is Man’s Best Friend. Rough-Draft #2 March 18, 2013 A Best Friend is Man’s Best Friend Dogs have been known to be “Man’s . Author And Hyde? Best Friend ” for thousands of years. More commonly known to be man’s best friends are dogs, rather than cats and any other animal. Most people consider a best friend as someone who is why beauty are good, there for you when you are sad or lonely, when you need someone to talk, cry, or laugh, however a man’s best friend is author and hyde, all the Essay, same and more.
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Some stay for a while and leave footprints on our . hearts. Of Jekyll? And we are never ever the same” (Unknown). What is oocl point to point, a “ best friend ”? Almost everyone has one, and almost everyone is author and hyde, one. Oocl To Point? There’s something about and hyde a best friend that cannot be duplicated. Everyone has their own definition of what their own best friend is like and what an conservation, impact he or she has made in their life. In this essay I would like to take a better.
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Stacie Oliker? Pretty name. she remarked instantly. This close friendship allowed me to come to know and experience a level of self disclosure like no other. With her I was and still am myself. Our high school friendship has unfolded. Ann Way , Friendship , Interpersonal relationship 1150 Words | 3 Pages. Narrative Essay Dating Your Best Friend I have a boyfriend who I have been dating for 7 months now; we started . Author Of Jekyll? out on to point February 12, 2011.
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That happens to 6th grade essay examples be my very best friend Maria Elena. Maria and I go way back! We already became friends in and hyde, kindergarten. Our mothers also started talking and comic and juliet that made it even easier for us to be friends . I remember when people asked me if I had siblings, and author and hyde I would always answer: “YES! I have a little sister”, because that’s what she is to me. We trust.
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Banana slug , Interpersonal relationship , Life 1041 Words | 4 Pages. Woman’s best friend . 44% of Americans own a dog. I have owned three dogs in my lifetime; three in water, which I no . longer own. Some say a dog is a man’s best friend , but to me, a dog is a woman’s best friend too. A dog is author, not just a friend though; it is part of the family. I have loved all of my dogs the same, but differently. Each one of the dogs that I have owned had their very own special personality.
Each dog meant something different to me; I had my first dog (Sammy), my best friend (Daisy). Dog , Dog health , Dogs 929 Words | 3 Pages. Compare and Contrast My Two Best Friends Are Like Twins. My Two Best Friends are like Twins Many people in the world have two best friends . Apa For Websites? . Some of them are so similar that it's shocking. They find some similarities in their attitude, personality or even interests. People may find similarities or differences in their best friends and some may not find any interests at author of jekyll and hyde, all.
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Organization of Paper: Title: Come up with a creative title Paragraph #1: Introduction. Use one of the “hooks” from the six choices on side 2. Don’t forget to let your reader know what your essay will be about (career, family, friends , relationships, house, and vehicle). Paragraph. Automobile , Dream , Henry David Thoreau 647 Words | 2 Pages. choose your major? 3. If you redo college again, what would you major in? 4. What course did you like the most? 5. What course did you like the and hyde, least? 6. . Why Beauty? How will your performance in your worst class affect your performance.
7. How would your best friend describe you? 8. How would your professor describe you? 9. How would your mother describe you? 10. Why are you applying for a job that you didn’t major in? 11. During college, how did you spend your summer vacations? 12.
What did you learn. 2006 singles , Computer science , High school 1570 Words | 6 Pages. DEATH OF A BEST FRIEND The school hall was quiet. Everyone was silent with their heads bowed down. No one spoke,laughed, giggled . Author Of Jekyll? or chatted. Apa For? There was just sorrow in the atmosphere. Few students could be heard sobbing while the rest just sat stone dead in their seats. What had happened? What was the cause of this sad and eerie situation? Why did she do it?
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Best friend becomes enemy. It was first day of author, summer. School almost finished. It was sunny and windy day. I was happy . that school almost finished. My friend and I were sitting at the park. We were planning how to why beauty pageants are good spend this long summer. George, my friend , gave me many plans for this summer but I didn’t agree with him. He was a lazy gay. Author Of Jekyll? His plan was: sleep till 11 a.m., and then play video games till 5 p.m. and then go to sleep.
He says that this must continue every day. . I Quit match , Father , Mother 1119 Words | 3 Pages. ? Friends Essay by Mitchell Scott Topic: What friendship means to me Friendship is a relationship that is needed in a society of . ours. With a demanding society where if you have no friends , it can be a tough time for you. Friendship is much more than just hanging around with your mates; it allows living to Single-Gender Classrooms be much more comfortable. Friendship is extremely underrated in a society of ours; we rely on author of jekyll our friends to have good times.
Sometimes you can’t imagine life without those who care for you. Comfort, Texas , Friendship , Interpersonal relationship 1072 Words | 3 Pages. ?Types of Essay And Examples Descriptive Essay : Someone Someone is a word you can use for anyone. Someone, Someone special, . someone you care, and someone you don’t know. Someone, that’s how I define him but not just that common someone, he’s someone who I treasure the relief, most. Author And Hyde? He is conservation essay, a guy who loves dancing. Author And Hyde? I can conclude dancing complete his life. He’s taller and older than me. He is so beauty conscious, especially when it comes to his skin’s color and his precious face. He has a cute little. 2008 singles , Debut albums , Family 842 Words | 4 Pages.
This entry is dedicated to my dad and he will never read it. Websites? Sad thing.* When I was 16 I had to write an essay in school about . the person I admire the most. Of Jekyll? So I wrote about my dad. My dad is not famous, nor is he rich or talented. Conservation Essay? He is not a scientist or a professor. Author? But he is the best man in my personal world even if he doesn’t know.
We never talk about emotional stuff, he never gives me good advice, actually we hardly talk. When my dad was young he was a biker. Motorbikes were his lifestyle. 2006 singles , Mother 940 Words | 3 Pages. MY IDEAL FRIEND I was walking home from school. I was carrying my books and tonnes of comic and juliet, homework home. I walked . Of Jekyll? with a heavy stride with my head hanging down, unaware of the chatter and 6th grade essay examples socialising going on around me. Spirits were low and I took my usual route home which usually takes me about 20 minutes. “What next? I have no idea what to do,” I told myself.
Abruptly, I knocked into something and all my books and papers fell to of jekyll and hyde the sidewalk. I lost my footing and went down on my knees. 2005 albums , 2008 singles , Debut albums 988 Words | 3 Pages. MAN'S BEST FRIEND - DOGS Why are we say that a dog is a man's best friend ? Before talking about . how important of dogs to our lives, we have to why beauty are good know where they come from. Dogs are domestic animals that humans first domesticated 15,000 years ago in the last Ice Age.
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Professor Neagle English 111 15 September 2010 We All Need Somebody to Lean On: My Ideal Friend According to Sharita . Relief And Juliet? Gadison, “Some friends come and of jekyll and hyde go like a season, others are arranged in our lives for a reason. “ Many might agree that good friends are hard to come across, so the ones that I consider good friends , I keep them close. Examples? I know without a doubt the qualities that make a good friend . And Hyde? A friend is someone who is dependable. When all else fails, it never harms to be able to oocl point have that. Friendship , Interpersonal relationship 1581 Words | 4 Pages. Book – my best friend Charles W. Author Of Jekyll And Hyde? Eliot said “Books are the quietest and most constant of friends ; . they are the most accessible and wisest of counselors, and 6th grade essay the most patient of and hyde, teachers.” Book is the best friend , a human being can have. Book is conservation, a friend that is never disloyal. Books are our friends for author of jekyll and hyde, life as because they never reject, never go or come, never fight and never blame us.
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WRITING THE COLLEGE ESSAY PURPOSE OF THE ESSAY Your GPA, class rank, SATI and SATII scores are all important to a college . admissions officer in helping to assess your academic abilities. But they are only Essay, numbers – they have no personality. What can make your application stand apart are the personal essays . The college essay will allow an admissions officer to look beyond those numbers and see you as a person. Of Jekyll And Hyde? A well-written essay should convey your thoughts, attitudes, personal qualities. College , Essay , Question 1382 Words | 5 Pages. Stacey Wilson October 14, 2011 Swrk 251 Social work value essay My mother likes to tell the story of why beauty are good, when I was four . And Hyde? years old going to why beauty my reading circle. While I was waiting for my reading circle to start, I noticed a baby crying so I picked up toys and started shaking them and making the author of jekyll and hyde, baby smile. For as long as I can remember I have always like to help others, I got enjoyment out of making my friends happy. Whenever one of my friends had a problem I was always there for them, to listen to.
International Federation of Social Workers , School social worker , Social change 2231 Words | 5 Pages. My best friend Everybody always has friend or friendship. Oocl Point To Point? There are a lot of kinds of . friends . We have friends , close friends and author of jekyll and hyde best friends . It is point to point, said a friend needs to be a good friend but it hard to find a best friend . Best friends need to of jekyll and hyde know about certain qualities of apa for, each other. Author Of Jekyll? Best friends are always there for pageants are good, you when you’re down or having problems. A best friend is the person you can always rely on and hyde for anything no matter what.
Best friends stick up for you even if you are wrong. Oocl Point To Point? . Friendship , Interpersonal relationship , Need 544 Words | 2 Pages.
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An Introduction to the Ancient Festival of Nowruz. Some people say that it’s the 5,774 th time that Iranians across the world are celebrating the ancient Persian New Year festival, Nowruz. However, some history experts believe that Nowruz has been enshrined and observed for more than 15,000 years, well before the official establishment of the Persian Empire. Like Christmas, Nowruz is an elaborate festival that brings millions of people together, but there are certain elements in Nowruz that make it a distinctive tradition, and one of these important elements is its historicity. Cyrus the author, Great, the first king of the Persian Empire, came to throne in 550 BC, but for almost 2000 years before him, when In-Su-Kush-Siranna was the ruler of the Kingdom of Aratta, Nowruz had been celebrated in Greater Iran, which consisted of several provinces that currently constitute modern countries like Afghanistan, Tajikistan, Turkmenistan, Azerbaijan, Armenia, Pakistan, Iraq, and parts of India and point, Turkey. Nowruz is author of jekyll, considered the most important national holiday in Iran as it marks the beginning of a new solar year and essay, the arrival of spring. According to the Persian calendar, Nowruz begins on the vernal equinox, which starts on March 20 or 21. The beauty and wonderfulness of Nowruz is that it starts on a unique moment each time and people excitedly and breathlessly wait for the announcement of what is known as the moment of the transition of the year. This moment is astronomically calculated according to and hyde the Jalali solar calendarand officially inaugurates the New Year. Unquestionably, Nowruz is Classrooms Essay, one of the prominent hallmarks of the Persian culture and Iranian civilization. It represents the glory and magnificence of ancient Iran and manifests a sense of national pride and dignity for Iranians around the world.
In his long epic poem, Shahnameh, the 10 th century Iranian poet and of jekyll, philosopher Ferdowsi talks in detail about the origins and roots of Nowruz. He says that when the legendary, prehistoric Iranian king Jamshid Jam conquered the world and ascended the throne, he declared that day as Nowruz and the beginning of Iranian New Year. On that day, Iranians from across the country would come to oocl point to point visit Persepolis (the ancient capital of the Persian Empire) to hold festivals, receive rewards and gifts from the of jekyll and hyde, king, enjoy eating festive meals of dried nuts, fruits, and sweetmeat, sing happy songs, and perform plays. Nowruz is in romeo, important in that it comes as winter ends, and author of jekyll and hyde, that is why Iranians believe Nowruz is a feast of rebirth and rejuvenation that injects fresh and warm blood into the veins of the frosty and frozen nature. Iran, which is famous for its climatic diversity and unique nature, is very beautiful in apa for the spring, and especially during the 13 days of author of jekyll Nowruz festivals. Fragrant flowers and attractive plants grow in large quantities in northern, central, and 6th grade essay, southern parts of Iran, and of jekyll, the weather is predominantly mild and why beauty pageants are good, moderate in the majority of the author of jekyll, cities all around the country. Nowruz is celebrated from the Farvardin 1 to 13 (Farvardin is the first month of the solar calendar whose name is taken from the Zoroastrian word “Faravashis” meaning “the spirits of the dead.” Iranians believe that the spirits of their deceased beloved ones will return to the material world in the last 10 days of the year.) One of the common traditions of Nowruz that the Iranians are strongly committed to websites is paying visit to author of jekyll and hyde the elderly and meeting the other members of the family. In such meetings, Iranian families entertain each other with delicious Iranian cuisines, spring fruits, dried nuts, candies, confections, deserts, rice-cakes, pastries, and cookies. Websites. Setting the of jekyll and hyde, “Haft-Seen” table is also one of the customs of Nowruz that is relief and juliet, seen as a quintessential part of the New Year celebrations. Haft means “seven” in Persian, and “seen” stands for the sign of the 15 th letter of Persian alphabet which sounds “s”. The Haft-Seen table is named so because there are seven items on this table whose name start with the Persian letter “seen”.
Each of these seven items signifies a certain meaning. Of Jekyll. These items include “Senjed”, or silver berry, the sweet, dry fruit of the lotus tree, which denotes love and affection; “Sumaq”, or sumac, the crushed spices of berries, which symbolizes sunrise and apa for websites, the warmth of life; “Seeb”, or red apple, which stands for health and beauty; “Seer”, or garlic, which indicates good health and author, wellbeing; “Samanu”, a sweet paste made of wheat and sugar that represents fertility and the sweetness of apa for life; “Sabzeh”, or sprouted wheat grass, which is a sign of renewal of life; and “Sonbol”, or the purple hyacinth flower, which represents prosperity and goodwill in the New Year. However, the majority of Iranian families put more than 7 items on their “Haft-Seen” table settings. The additional things are “Sekkeh”, coins that herald wealth and affluence; “Serkeh”, vinegar that symbolizes age, patience, and the toleration of hardships; and and hyde, “Sangak”, a plain whole wheat sour dough flatbread that characterizes blessing and good luck. Relief In Romeo And Juliet. Iranians also put colored eggs and a bowl of goldfish on author of jekyll their traditional Haft-Seen table and consider these two elements as signs of fertility, welfare, and happiness.
One of the other elements placed on the beautiful Haft-Seen table is a mirror, a symbol of purity, reflection, and honesty. Iranians never forget to put a beautifully adorned and decorated mirror on their traditional table setting. They also put a copy of the oocl point to point, Holy Quran on their Haft-Seen table, which they believe will guard their life in the coming year. In an elaborate and well-researched article about Nowruz published on the Iran Review website, the author of jekyll, cultural researcher Firouzeh Mirrazavi writes, “The festival, according to apa for websites some documents, was observed until the fifth of Farvardin, and then the of jekyll, special celebrations followed until the end of the month. Possibly, in the first five days, the festivities were of a public and national nature, while during the rest of the why beauty are good, month it assumed a private and royal character.” Since Nowruz was historically celebrated in Iran’s ceremonial capital Persepolis [Takht-e-Jamshid] in the southern city of Shiraz, every year thousands of Iranians travel to Shiraz to take part in the national celebrations of author of jekyll and hyde Nowruz. Point To Point. Even the foreign tourists who travel to Iran to take part in the celebrations prefer to visit Shiraz or Isfahan during the 13 days of Nowruz. But why is author of jekyll, Nowruz extended for 13 days? According to the ancient belief of the Iranians, 13 is an inauspicious number. On the 13 th day of Farvardin, Iranian families gather in parks, gardens, farms, and other green places to Essay eat cuisines containing certain local herbs and have friendly conversations. They also throw sprouted wheat grasses into rivers believing that by leaving the “Sabzeh” in the waterways, they throw away the misfortune associated with the number 13 and the 13 th day of the year, and this way, they guarantee their New Year and prevent hardships and calamities from coming into their life. They think that the Sabzeh that is pitched into the rivers will take the bad luck with itself to an unknown destination.
In Nowruz, the adults in the family pay the author and hyde, younger members certain amounts of cash as a gift for the New Year. This reward is called “Eidi” and is not usually spent during the whole year but saved and kept as a token of blessing and wellbeing. Websites. With all of and hyde its beauties and splendor, Nowruz is now considered a global festival as it was officially recognized and registered on the UNESCO List of the websites, Intangible Cultural Heritage of Humanity in February 2010. The same year, the UN General Assembly recognized March 21 as the International Day of Nowruz, describing it as a spring festival of Persian origin which has been celebrated for thousands of years. Nowruz is a relic of author past days, a remnant from the dawn of human civilization. It removes religious, cultural, lingual, and point, national boundaries and connects the hearts of millions of people who want to of jekyll take part in a unique ceremony marking not only the beginning of New Year, but the end of the distressed winter and arrival of the delightful spring. It’s not simply a source of honor for Iranians who observe and celebrate it, but an opportunity for the congregation and solidarity of all the peace-loving and peace-making nations around the world. Kourosh Ziabari is an award-winning Iranian journalist and reporter. He has won three prizes in 6th grade essay Iran's National Press Festival. In August 2015, he was named the recipient of the Senior Journalists Seminar Fellowship by the Hawaii-based East-West Center. In June 2015, he was selected by Deutsche Welle and European Youth Press to be part of a team of 16 young reporters and journos from different countries covering the Global Media Forum 2015 in Bonn, Germany.
Kourosh is also the author, recipient of the Gabriel Garcia Marquez Fellowship in Cultural Journalism 2015 by the FNPI Foundation in Colombia. Kourosh is a staff writer and reporter at Iran Review. He is the Iran correspondent of Fair Observer, an international media corporation based in California. He writes for The Huffington Post, Your Middle East, Middle East Eye and International Policy Digest. Follow him on Twitter at @KZiabari.
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Provided WEB Based Engineering Design Services doing Schematic Capture and author, PWB Layouts of Essay PLC Interfaces using OrCAD. Performed various Test Engineering activities. Author And Hyde! Involved in assessing and performing the overall Functional and In-Circuit Test activities in the production and repair of the why beauty pageants, DC-40 Handheld 486 Datacomputer w/LCD Display, PCMCIA I/F, Irda I/F, Modem I/F , and associated Power Supply SMD Assembly. Performed evaluation and refinement of author of jekyll and hyde a variety of Functional Test operations, debug analyses and recommended solutions to improve the to point, production through-put and provide fully tested hardware to the customers of contract manufacturing firms. Created Final Test Procedure for of jekyll, the Nortel 1800 Chassis and Modules Communication System Card PC603 Based, Modem Assembly w/SMD Modem Daughter Cards. Documented and 6th grade, Performed Functional Test Procedure for author of jekyll and hyde, TELCO Communication PWB Modules, WATERS Corporation PWB Module and a variety of Single-Gender MKS Sensor SMD Assemblies. ADVANCED SYSTEMS CO., Pillsbury MA. Senior Development Engineer 1992-1998. Electronic Design Laboratory Lead Engineer and Cost Account Manager.
Provided upper management monthly Progress Reports and Weekly Departmental updates. Interacted with all required government customer agencies, Program Management Office, Manufacturing Engineering and other Design Laboratories to meet corporate objectives and deadlines. Managed and of jekyll and hyde, participated in Electrical Engineering involved in the specifying, designing, development, testing, debugging and qualifying prototype Electronic H/W. Responsible for the daily technical operation and security functions of the why beauty pageants are good, DoD Closed Area Digital Laboratory Central Test Facility. Upgraded and maintained PATRIOT COMO Simulation Laboratory.
Technical Integration Lead to an engineering group of 10 engineers, in both hardware and software. Incorporating, integrating and of jekyll, testing PATRIOT COMO I/II Telecommunication Upgrades supporting electronic assembly upgrades through Manufacturing and Depot Integration. Technical Lead Integration Test Engineer for the Radio Logic Routing Unit-Upgrade Integrated and tested a number of VMEbus designed Modules i.e.SBC, SIO, EPROM, ethernet supporting the in romeo and juliet, RLRU-U transition to production and on through qualification testing at and hyde Field Sites. Apa For! Technical Lead Electrical Engineer for PATRIOT COMO UPGRADES participated and provided input to System, Concept, Equipment, Readiness and Production Reviews. Assistant Subcontract Manager for Smart Matrix Unit GTE and Lightweight Computer Unit SAIC integrated, tested and qualified into PATRIOT COMO. Development Engineer 1990-1992. Electronic Design Laboratory Lead Engineer and Cost Account Manager for TACIT Rainbow Mission Computer TRMC . The TRMC is based upon a MC68030 with dual MC68332s along with two subsystems interface modules and a power supply. Supervised and directed four Electrical Designers. Participated and provided Technical Engineering Support to System, Concept, Equipment, Readiness and Production Reviews transiting the TRMC Design into a solid Product with the help of Concurrent Manufacturing Engineering. Developed requirement Specifications, Concept definitions, analyses and performance trade-offs of various system architectures. Generated Assembly Dwgs., Parts List, Detail Dwgs., Altered Item Dwgs., Component Spec/Source Dwgs., Electrical Schematics, Interface I/O Documentation,PWB Artwork, PWB Mechanical Dwgs. Author Of Jekyll! as required.
Built, Serviced and Maintained the TACIT RAINBOW Software Development Facility, integrated prototype H/W along, with SPARC Workstations, IBM-PCs and oocl, Silicon Graphics Workstations in the performance of software code development, system simulation and author and hyde, software performance evaluations. TRMC 80 Logic in apa for websites Altera FPGAs No PWB Design Errors. Directed Multiple Laboratory and Manufacturing resources into author, developing a fully integrated, form-factored and tested unit which was integrated into apa for, the TACIT RAINBOW Missile Prototype and Tested using LABVIEW. Senior Electrical Engineer 1987-1990. Digital Design Laboratory Lead Engineer and Cost Account Manager. Provided upper management monthly progress reports and author of jekyll, weekly departmental updates.
Assigned design tasks and Single-Gender, maintained cost and schedule. Lead Engineer for MIL-STD-1760 Missile Simulator Unit MSU 68020 based simulated aircraft stores interface for F15/F16/F18. Author Of Jekyll! Provided User Interface ports Monitor, Serial and apa for, Parallel Printer interfaces. Author Of Jekyll! Tested and qualified to MIL-STD-810C 12 units. Lead Engineer for Missile Integration Test Set MITS Integrated, incorporated and tested Short Round Test Set into MITS H/W to provided Full-Up Missile Test. Lead Engineer for Dynamic Software Test Facility DSTF for software development designed, developed, integrated and water conservation, tested a facility based upon five MC68020s, simulated internal missile interfaces via specialization circuitry and utilization of and hyde Personal Computers. Electrical Engineer 1986-1987.
Module Design Engineer responsible for all components of the apa for websites, Module Design Process. Coordinated and author, supplied technical design input, integration test and apa for, operational inputs for innovative subsystem development. Redesigned the author and hyde, Digital Signal Processor and upgraded Missile H/W turning TTL Logic into Gate Array Logic using reverse engineering techniques. Designed and Supported two Missile PWBs using MENTOR, one a Data Acquisition Module 25 Analog/75 Digital and Single-Gender Classrooms Essay, the other a Aircraft HOW Interface Module 50 Analog as part of Low Cost Seeker Program HARM. Engineering Specialist 1985-1986 Specializing in Motorola Microprocessors incorporation, integration testing. Designer for and hyde, Drop Test Seeker DTS Program Zilog Z8002 based Integrated Custom 10K Gate Arrays with Micro-Wire Technology using MENTOR and VHDL PWB Designer of Pre-Amplifier Module 100 Analog using PSPICE and apa for, MENTOR Proposal Engineer for US Navy Outer Air Battle Program. RADMEX Inc. Boston MA. Senior Electronic Design Engineer.
Performed and Specified the Electrical Design, Electronic Circuit Prototyping, PWB Layout, Product Documentation, H/W Development, Integration and Testing of author a Computerized Newspaper Pagination System for a start-up company. Product Line developed and comic and juliet, marketed was the Breeze Workstation , BitCaster Data Controller , BitPrinter Printer , BitSetter Typesetter and BitPlater Laser Platemaker . Involved in of jekyll all phases of electronic and product design, S/W H/W integration, test, production implementation, field service and marketing. Design/Developed a Raster Image Processor based upon in romeo and juliet, the AMD2903 Bit-slice processor form factored on a 12 x 12 multi-layer PWB using inverse euro-connectors. Designed/Developed a Micro-Controller AM2910 with extensive memory, which produced a 96-bit microword form-factored on a 12 x 12 multi-layer PWB. Developed unique high-speed clock using PAL Logic. Used Future Net and Multi-wire prototyping. Designed/Developed a Dual Port Module on a two-sided PWB using light table, which allowed the and hyde, i ncorporation of a wide range of Off-the-Shelf Multibus I Modules.
DAYNEON COMPANY, Bedford MA. Test Engineering Aide. Worked in the Missile Integration and Test Department of the Missile Guidance Laboratory while attending NU. Comic Relief And Juliet! Assisted in the integration and testing of the prototype AMRRAM Missile. Involved in the development of a Missile Readiness Test Set MRTS . Responsibilities included: Creation of of jekyll and hyde overall MRTS System Level Diagrams; Generation of Schematics, Part List and Wire Lists; Assembly Drawings.
Oversaw building of unit and performed engineering inspections;Performed initial testing and qualification testing. PANAMETRICS Inc., Waltham MA. Design Engineering Aide. Under direction of Physicist and Electrical Engineers worked as a member of the Radiation Physics Laboratory while attending NU. Performed tasks in Prototyping, Development and Testing of various, Satellite Subsystem H/W for essay, GOES Program. Held various jobs while attending college. Worked as Security Guards, Cashier at Store24, Retail Sales at and hyde Building 19 3/4, Bottling Production Line, Electro-Plating Operator, and Warehouse Laborer. Had own summertime Painting and Landscape Business. 1981 NORTHEASTERN UNIVERSITY US-MA-BOSTON.
Bachelor s Degree BS ENGINEERING TECHNOLOGY. 1976 Sylvania Technical School US-MA-Waltham. Certification COMPUTER ELECTRONICS. 1974 UNIVERSITY OF MASS US-MA AMHERST. Courses PSYCHOLOGY/CRIMINAL JUSTICE. ELECTRICAL ENGINEER/TECHNICIAN with extensive hands-on experience in SYSTEM DEBUG COMPONENT LEVEL TROUBLESHOOTING, ELECTRO-MECH ASSEMBLY, with WIRE-WRAP AND SOLDERING EXPERTISE.
Expertise with Microprocessor/DSP/Embedded Designs AMD, Motorola, Intel, TI ;Analog Design, RF Design, High Speed Digital Circuit Design; FPGA/PAL Logic Xilinx, Altera, Actel ; VHDL; Multilayer PWBs and SMD Assembly, EMI Design Techniques, Backplane Design Multibus I/II, VMEBus, ISA, PCI Bus Serial I/F: RS423, RS232C, RS422, RS485 PARALLEL I/F; 1553B I/F, IEEE-488; LCD Displays,PCMCIA I/F, Irda I/F, Modem I/F, SCSI1/2/3 I/F; Ethernet, Fiber I/F; Optics, Integration of examples a variety of computer hardware; Familiarity with Test Equip./ATE. PROJECTS, WORD, EXCEL, POWERPOINT, MENTOR Schematic Capture/Logic Simulation, PSPICE, CLARIS DRAW, MENTOR PWB LAYOUT, OrCAD,WINDOWS w/LABVIEW, MATHLAB; Assembly C Programming. DIGITAL TECHNOLOGIES, San Jose, CA. Involved in author of jekyll and hyde Ethernet/firewall product development for the OEM customer base. Designed the and juliet, architecture for author, the current ASIC Ethernet hub/switch. This SOC included an ARM 7 processor, 5 MACs, a Triple DES core and 24K of Dual Port SSRAM using .25-micron technology.
Headed the design team in the implementation of the chip. VHDL was used for the design implementation. Designed the board level firewall product that uses this ASIC. Implemented a Triple DES core into an Actel FPGA that was used on the low-end firewall product line. Designed a three-channel Fast Ethernet firewall controller using an Intel ARM 9 processor and an ITE PCI bridge. In charge of engineering development of 6th grade essay board level designs for both product and OEM reference. Additional engineering responsibilities include: Wrote specifications for both chip and board level products. Wrote guidelines for PCB layout that encompasses component placement for high-speed signals and FCC compliance testing.
Incorporated manufacturability into of jekyll and hyde, designs including ATE. Developed and maintained project schedules. Interfaced with the software department for BIOS and POS functionality. MIRRENFAX IMAGE PRODUCTS, Sacramento, CA. December, 1997 to Single-Gender Essay February, 1999.
MANAGER OF ENGINEERING. Manager of the hardware engineering team. Of Jekyll! Involved in product planning for a new family of comic relief in romeo and juliet OEM image processing controllers. These controllers are installed in high-end scanners and allow Virtual Rescanning while automatically changing the image characteristics deskew, thresholding, intensity, cropping, etc. . Responsibilities include interfacing with scanner manufactures during product definition, scheduling of product development, resource management, project management, ASIC vendor selection and CAD tool evaluation and purchasing decisions. Involved with defining the next generation Image Processing ASIC. Responsibilities included defining functionality, project management, and vendor coordination.
Also, designed the of jekyll and hyde, system architecture for a second ASIC that became the conservation essay, system intelligence. This contained an of jekyll embedded ARM7 processor, PCI interface, DRAM, etc. Led the design efforts on this second ASIC. Both ASICs were in the 1M to 1.5 M gate range and implemented in .25-micron technology. VHDL was used for the design implementation. Designed several controller boards that used these ASICs for different scanners. CMD TECHNOLOGY, Sacramento, CA. June, 1995 to December, 1997. MANAGER OF ENGINEERING. Managed the Raid Division engineering team.
Responsibilities included scheduling, budgeting and product development for both board and system level Raid products. Involved in defining the next generation architecture of Raid controllers that was comprised of a four ASIC chip set. Project Manager for a Digital Equipment Corp. specific Raid controller. This project was a joint effort between CMD and essay, Digital with CMD designing the controller and Digital doing the mechanical packaging. Responsibilities included coordinating the hardware efforts between the two companies along with designing a FPGA that interfaces to Digital s EMU and Fault Bus. Designed the Raid controller board that was used by Digital. Author Of Jekyll! Designed several other Raid controller boards that were used for the OEM market. Member of the Change Control Board CCB and the Advanced Products Group. Involved in implementing procedures between Document Control and Engineering.
CORSER CORP., Costa Brava, CA. May, 1992 to 6th grade June, 1995. Involved in the design of a DAT tape controller ASIC which interfaced to a SP1 format tape drive. This ASIC was implemented in .8-micron technology. Author! Designed the next generation DAT tape controller ASIC. This chip was implemented in .6-micron technology and has approximately 80K gates.
Designed the tape controller board that uses the new ASIC along with a Data Compression/SCSI ASIC, V50 microprocessor, 1 MB of DRAM buffering and water conservation, FLASH EEPROM. Joined the Arcuate Scan Tape group and designed an ASIC used in controlling the tape head preamps. Author! This ASIC was mounted to the head assembly using chip-on-board technology. Also designed the Servo Gate detection ASIC used for head positioning. Why Beauty Pageants Are Good! All ASICs designed and simulated at Conner were done using VHDL.
IRVEL CORPORATION, Scottsdale, Arizona. December, 1988 to author April, 1992. MANAGER OF ENGINEERING. Management responsibilities for engineering, software, and test departments. Established procedures in top-down design methodology and functional specifications for the Software and Hardware Departments. This provided a path for designs with a high degree of modularity and ease of software/hardware integration. Apa For Websites! Defined future products and initial marketing strategies. Designed a proprietary Error Detection and Correction ASIC to be used in memory intensive products. Author! A 16 and 32 bit version of this ASIC was designed in 1-micron technology and consisted of 34K gates.
CAD tools used in these ASIC designs include Cadence for schematic capture and Verilog for water essay, simulation. Also designed a PC compatible memory board that incorporated this ASIC. Developed specifications, in conjunction with IBM Boca Raton, Florida , for a high performance PS/2 memory board. Author And Hyde! Involved in setting up incoming test procedures for partial memories using a Teradyne tester. Two patents emerged from the research of memory subsystems. FUTURAMA, Sacramento, CA. October, 1984 to November, 1988. PROJECT MANAGER/SENIOR ENGINEER. Involved in writing product specifications for an advanced system architecture that was incorporated into a microprocessor development system. Interfaced with the software development group to identify areas of concern when porting UNIX on to the new system. Designed a 68000 based CPU board for this development system.
During the water, design phase of the author of jekyll and hyde, CPU, research was done on interfacing a 68000 to various memory management techniques along with different bus structures Multibus, IEEE 896, and VME . Designed the system protocol that provided an efficient means of communication between the CPU and intelligent, DMA driven, I/O controllers. Designed an intelligent SCSI controller that used this protocol. TRIANON CORPORATION, Sacramento, CA. March, 1981 to October, 1984. PROJECT MANAGER/SENIOR ENGINEER.
Project Manager for the Mark III minicomputer. Responsibilities included managing an engineering team and coordinating the software and manufacturing departments efforts on the project. Designed the hardware and firmware for the Mark III Peripheral Interface Board that contained a tape streamer interface, four asynchronous ports and a two-port SMD/CMD disc drive interface. The Peripheral Interface Board was designed using discrete logic and incorporated the 2903 bit slice architecture for the micro-engine. Comic In Romeo And Juliet! The firmware consisted of 32 bit-wide microcode. COMPUTER AUTOMATION, Sacramento, CA. June, 1977 to author of jekyll March, 1981. Engineering team member involved in the development of essay a new processor and author, the related I/O controllers.
Designed the essay examples, interface protocol and an I/O relay controller for author and hyde, this processor. This team was located in Dallas, Texas. Previously: Designed a debug module including hardware and firmware that could be used for debugging Z80 software. There was also a 32-channel trace for storing address, control, and data lines upon comic and juliet, receiving a pre or post trigger. Of Jekyll! The back-end contained the in romeo and juliet, necessary handshaking to a modem so the board may be used remotely from the operator. Initial assignments upon joining the company involved sustaining engineering hardware and firmware for a disc drive controller, synchronous communications controller, MOS memory board and static problems with CRT s. BSEE, California Polytechnic University, San Luis Obispo, California, 1977.
Concentration in Computer Systems. Will be furnished on request. Six years of author of jekyll and hyde strong experience in Classrooms research, analysis, design, development of instruments using VHDL/VERILOG, ASIC Design, FPGA design, digital design techniques, design using microprocessors and micro controllers. Author Of Jekyll! Expertise in design and simulation of electronic circuit boards using orcad, spice, circuit maker and smart work. Expertize on Active HDL simulation package. Languages: C, C++ Application: FPGA, ASIC design, PCB design, Digital and analog circuit design Tools: Xilinx, Xilinx FPGAs xilinx 4000XL series, XILINX VIRTEX series , Cypress. Hardware Definition Language HDL : Verilog, VHDL, 8051 assembly HDL Tools: ModelSim VHDL, Leonardo Spectrum, RAD51 assembler, ORCAD, Spice.
Compiler: AVC51 Operating System: Unix, Windows NT/95/98. Digital Automatic Moisture Computer. September 2001 - Till date. Development of examples a stand alone device to measure moisture content of various agricultural products. Involved in Design and development of automatic moisture meter both independent and author and hyde, computer interfacable.
First prototype developed around 8051 microcontroller using AVC 51 for embedded system. Involved in sensor design. Design and Single-Gender, coded same using C. Handled design and and hyde, fabrication of analog and digital boards for first prototype. Second prototype being developed as full custom SOC System on chip for the calibration circuit around microcontroller 8051using simulation and synthesis tools of mentor graphics. The input taken by sensor directly displayed in terms of percentage moisture. Development of calibration technique based on method of least squares. Writing source code and test benches in VHDL for interfacing of oocl point 64K RAM, ROM, decoder and author of jekyll, their interfacing with the A/D converter and PGA. Simulation of calibration process and verification of Single-Gender Essay functionality and timing errors for of jekyll and hyde, same. Synthesizing code on Xilinx virtex series using Xilinx FPGA.
Environment: RAD51 assembler, AVC51, Mentor graphics, VHDL, Modelsim and Leonardo Spectrum, Xilinx, Virtex, Windows NT. Central Scientific Instruments Organization. 8 BIT Microcontroller ASIC Design Engineer. Involved in design of a 8-bit micro-controller having features of INTEL 8051 microcontroller. The FPGA consists of 128K RAM and 64k ROM and is instruction compatible to the Intel 8051.Prepared library package for the instruction set of the microcontroller in VHDL. Wrote source code for the ALU to perform various arithemetic and logical opeartions. Source code for comic relief in romeo and juliet, the RAM and ROM entity was written and debugged using test bench generation schemes. A complete model of the FPGA was designed using the above logical blocks and the design was implemented on Xilinx VIRTEX FPGA. Of Jekyll! a memory mapped output port was also added to the design. Environment: VHDL, Intel 8051 training kit, mentor graphics software , synopsys , Xilinx tools. Central Scientific Instruments Organization.
Microwave Oven ASIC Verification Engineer. Involved in the design of high frequency switching circuit to Essay operate at 2.5 GHZ using spice simulation software.Involed in counter design for the programmable counter for author of jekyll, the magnetron switching circuit. Involved in debugging, verification and analysis of critical timing parameters for low power consumption and area size using Mentor graphics Leonardo spectrum synthesis tool . Synthesized circuit around rtl resistor transfer level after calculating timing delays and to point, critical path parameters. Environment: Spice simulation software for mixed mode signals, Mentor graphics simualtion and synthesis tools. Department of of jekyll and hyde Science and Technology DST. Video Chip simulation ASIC Verification engineer. A VMIS Video million images per second embedded processor was studied and was simulated for various digital applications. Captured top-level video inputs simulation of VMIS video million images per second TV controller chip having an embedded processor. Enabled signal processing for digital applications. Worked in in romeo and juliet a team for simulation of chip. Of Jekyll And Hyde! Carried out chip verification using using tools from mentor graphics.
Verified ASIC for water, rtl resistor transfer logic syntax and semantics. Used Configuration Management Tool for database version control. Environment: Embedded processor from author and hyde, sigma Electronics, Mentor graphics tools, VHDL, Windows 98. Technology mission for oil seeds and pulses. Sept 1998- June 1999. NIR Near Infra red BASED CEREAL / GRAIN ANALYSER Hardware engineer. Selected photodiodes according to wavelength of why beauty pageants various samples to be measured for different parameters.
The selection of photodiodes was done to author of jekyll and hyde opearte at oocl point to point radio frequencies. Designed analog and digital board around SPICE simulation software. Interfaced memory and of jekyll and hyde, display using embedded system programming using AVC 51, RAD 51 around microcontroller 8051. Further, an FPGA was developed to apa for perform the application of microcontroller 8051 and the entire calibration circuit was interfaced around the Xilinx FPGA. Of Jekyll And Hyde! Coded using VERILOG. The digital circuit associated with ROM, RAM, decoder,latch was implemented with the developed Xilinx FPGA microcontroller . As a team member wrote source code for the FPGA microcontroller features and tested the apa for, functionality of interfacing circuit and simulated it using modelsim VERILOG. Environment: Microcontroller 8051, AVC51 and RAD51, Spice, Mentor graphics tools, model sim, Leonardo spectrum, Unix shell scripts. Department of Science and Technology DST. CPU Central Processing Unit Design ASIC Design Engineer.
Designed and developed a 8-bit microprocessor. The device consists of author a RAM, ROM, a high speed ALU, shifting, decoding and multiplexing circuitry. Made package for the instruction set of 6th grade 8085 in VHDL. Wrote source code for and hyde, the ALU to perform arithmetic and logical operations using VHDL, source code for the RAM and ROM implementation. Simulation of the are good, functionality of the processor using test benches on and hyde Active HDL simulation package in Window NT environment. synthesized the essay, same on XILINX FPGA. Environment: Active HDL, Vinytics 8085 microprocessor kit, Xiilinx spartan series,Windows NT. Technology Mission of Oil seeds and author of jekyll and hyde, Pulses. Digital aflatoxin meter Test Engineer.
Designed electronics related to to point system around ORCAD IV , checked for the functionality of the design using mixed mode signal simulation around ORCAD IV and development of calibration software around microprocessor 8085. Documented instrument for transfer of know how and providing intensive training to user on how to use same. Environment: ORCAD IV, Vinytics 8085 kit, assembly programming for 8085. Department of science and technology. Sept 1996- March 1997. Gold Analyzers Test Engineer. Developed analog and digital electronics design circuit board using ORCAD.
Checked the functionality of the same and its interfacing with the sensor. Documentation of instrument. Involved in selection of principle of purity measure using non-destructive technique based on energy dispersive X-Ray fluorescence spectrometry. Environment: ORCAD Version 1V, Windows 98. The projects around VHDL were coded and author of jekyll and hyde, tested before synthesis and also associated with PAL Programming, analog and breadboard testing. Responsible for integration and test of a UART, real time clock, keyboard controller, DMA controller and interrupt controller chip. This helped in gaining good understanding of ASIC design and verification methodologies along with PAL and conservation essay, FPGA programming. Author! Responsible for working with clients on intensive short term methodology training.
Responsible for training students in VHDL, synthesis and methodology. Aid in adaptation of training materials and development of new training classes. Paper publications and presentations have been made on Digital Automatic Moisture Computer and Capacitive moisture measurement of grains and oil seedsin various national journals. Conservation Essay! Training has been imparted to various engineers and of jekyll, students of engineering colleges from websites, time to time. Author! Significant contribution in organization of water various seminars and conferences related to instruments developed, various projects for water quality monitoring and soil analysis have also been designed and developed. B.S. in Electronics Engineering. Assume a role in author ASIC Verification/Applications/Design Engineering. 4+ years experience in the EDA Verification Industry.
Senior Project Engineer (Promoted from Applications Engineer) Technical Lead for a TtME (Time to Market Engineering - a design verification consulting service) project for a Germany based company. Successful completion of the project lead to Single-Gender Essay the sale of an author and hyde emulation system. Verified a 2+ million gate ASIC design. Assisted in project startup, Assessed project needs for verification and implemented design optimizations (for environment, RTL level and simulation). Executed project milestones such as running RTL design (Verilog and VHDL) through synthesis and pageants are good, simulation, providing training implementing Cadence verification tools on site. Used test benches for passing vectors and debugging simulation differences.
Implemented Verification Flow. Identified introduced Cadence tools to the Verification process. Advised on design methodology and validated the subsequent setup. Lead Engineer for a European account (Philips - HDTV division): Consulted on Verification flow, and author, provided optimization ideas. Offered on site support and tool integration. Implemented a synthesizable cycle based design and test bench, and helped with the execution. Assisted in customer evaluation (San Jose based IC design company for DTVs) for a simulation acceleration beta product.
Worked with verification engineers to write optimized test benches. Worked on a product evaluation with Ericsson, Sweden, that resulted in sales for numerous simulation software licenses. Worked closely with Quickturn RD and a third party RD (Verisity) that provided the testbench generating tool. The customer desired a combined product of 3 verification products along with a testbench generating tool. Worked with QT and Verisity s RD to Single-Gender Essay integrate all of these products. Author Of Jekyll And Hyde! Provided post-sales technical support and worked to increase the simulation performance. Used profiling tools to determine simulation speed bottlenecks. Implemented RTL and C model design changes for maximum performance optimizations. Essay! Successfully completed a TtME project with Ericsson, Germany, over a four-month period. This involved remodeling (in Verilog) significant portions of their design, testbench and memory models to be cycle based. Debugged differences in simulation results between Speedsim and the customer s internal simulator.
Successfully completed a two-month TtME project with Cabletron. Support included consulting on testbench methodologies, creating a synthesizable testbench, remodeling LSI memories to be cycle based, and making the LogicVision environment compatible to and hyde Speedsim. Essay Examples! Assisted the Quickturn India Distributor with a customer evaluation. Responsibilities included going on site and using test bench methods, passing vectors for author of jekyll and hyde, showing proof of apa for websites Speedsim functionality and performance on their design. Provided training to Application Engineers on topics related to simulation/acceleration tools during boot camps and author and hyde, other training sessions. Worked on numerous customer benchmarks which required verifying 1+ million gate ASICs with Quickturn/Cadence lint checker, synthesis, simulation, acceleration and emulation tools. Presented demos and presentations at DAC 98 and DAC 00. Corporate Technical Support Specialist:
Provided technical support for essay examples, all of Quickturn s Simulation/Acceleration products. Clients included Ericsson, Intel, IBM, Lucent, AMD, Fujitsu, Philips and Mitsubishi. Played a product specialist role, with responsibilities including: Supporting Customers Quickturn Application Engineers: coordinating and resolving software, hardware and design related issues, problems, bugs and questions. Providing workarounds to customer issues and of jekyll and hyde, working with RD to get critical customer bugs fixed as soon as possible. Was hired as ASD s (advanced simulation division of Quickturn) very first technical support specialist for Speedsim. ATRA Corp., Bayer Inc. Co-Op Internship (full time) Modeled a MC68HC11E9 Microcontoller Unit in point to point VHDL.
The unit included microprocessor and memory components. Author And Hyde! Implemented design and verification with the help of ViewLogic tools like ViewDraw, ViewSim and Essay, ViewTrace. M.S, Electrical Engineering, University of Massachusetts, Lowell, MA Dec 96. B.S., Electrical Engineering, Regional Engineering College (REC) Surat, India Aug 94. Expertise in author of jekyll Cadence Simulation, Acceleration and Synthesis Tools. Experienced with ViewLogic Schematic, Design and Waveform Viewer tools. Simulation software: Powersuite, Speedsim, Megasim, PowersuiteVHDL, SPICE Emulation/Simulation Acceleration Cobalt, Radium, Palladium DAI: SignalScan, CompareScan Novas: Debussy Mentor Graphics: MTI View Logic: ViewDraw, ViewSim and ViewTrace.
Strong Verilog skills, VHDL, C, Unix, Perl. References available on Classrooms request. ASIC PHYSICAL DESIGN ENGINEER. To achieve excellence, to be resourceful and optimistic and to pursue a challenging career in VLSI design. Area of author of jekyll and hyde specialisation : ASIC Design Flow and Methodology, Simulation, Synthesis, Floor plan, Place Route, Timing Verification, CTS. Summary in examples short : Have got more than 20 months of experience in the field of author of jekyll and hyde VLSI. Essay! Worked in logical design for 8 months rest in physical design. Moreover i have done my academic project in VLSI field. Arsanti!
Software Development Center(I) Pvt Ltd. Design Service Engineer(Physical design) Creating various test cases Benchmarks for customers. Author! Used to Essay create testcases for QA of of jekyll and hyde Avanti tools. Creating testcases to check various releases of Avanti tools. Clearing Customers doubts queries regarding design tools. Vdesign Training development Centre Pvt lt. Trainee Design Engineer.
Responsiblities : Logical design Digital design. Writing Verilog codes for various small Designs. Writing Test benches for Essay, designs. Author Of Jekyll! Writing Scripts to check the designs. Undergone training on FPGA/ASIC design flow(logical design) and methodology,HDL coding for comic relief in romeo, circuit implementation and test bench,simulation, timing Verification,Floorplanning,Place Rout (Vdesign Training Development Centre, PondyCherry). Undergone training on ASIC design flow(Physical design), Datapreparation, Floorplan,Place Route,timing, Physical Verification(DRC LVS). (Time To Market Ltd, Secunderabad). Projects carried out: (Physical Design) Design Specification: Hierarchical design with 5 softmacros. Hierarchial Floorplanning of Top Cell with core utilization of 75%, alongwith floorplanning of each soft macros with utilization of 80%. (Tool used Planet PL ApolloII) Timing Driven Placement of each soft macro with constraints from Synopsis Design Constraints(SDC). (Tool used ApolloII Saturn) Clock Tree Synthesis (CTS) of of jekyll eachsoft macro with a target of skew of 0.2ns and phase delay 0f 2ns.
The CTS is carried out for the Top Cell also. (Tool used ApolloII). Routing of each macro and the Top Cell. (Tool used ApolloII). Physical Verification for DRC LVS for water conservation, each macro and the Top Cell. (Tool used Hercules). Company : TTM( as a part of training program in Physical Design) Designing of Standard Cells of author of jekyll 0.24 technology along with DRC LVS check. (Tool used Enterprise Hercules) Die Reduction Power Analysis : With a core utilization of 6th grade 98.5%. Contains 19 hard macros, and 28k standard cells. (Tool used ApolloII Mars-Rail) Timing driven :Flat design with an initial slack of -61.3, and congestion overflow of author of jekyll 4.03%. (Tool used ApolloII Saturn)
BenchMark For LSI logic involving diesize with 30k std cells with core utilization of 96%. BenchMark For LSI logic involving Congestion driven placement with a core size of water 26,000,000 micro^2. Author Of Jekyll! Bench Mark for Teralogic involving timing with Tristate Nets High Fanout Nets with timing specs difficult to meet. Bench Mark for Teralogic involving Design Planning starting from 6th grade essay, synthesis to Global rout Its mearly an analysis. (Tools used for above BM's: Apollo, Saturn, MilkyWay, JupiterP) EIGHT-BIT MICRO CONTROLLER. DESCRIPTION: The microcontroller which is the true computer on chip.The design incorporates all of the author and hyde, features found in a microprocessor ie. Essay Examples! CPU,ALU,SP,PC,genaral purpose registers and special purpose registers.It also has added the other features needed to make a complete computer ie.ROM, RAM, parallel port, serial port, counter and author of jekyll, clk circuits Like microprocessor , microcontroller is to point, a general purpose device but one that is meant to read data, perform limited calculation on that data and author and hyde, controls its environment based on these calculation. TEAM SIZE : 7 members. DURATION : 3 months. MY PARTS : CPU, counter timers, Interrupts, ROM and RAM.
POLARIS for simulation. EXPLORERTL for RTL analysis. RTL MODEL OF FOUR BIT MICROPROCESSOR : DESCRIPTION: This four bit processor consists of the following components such as multiplexer, program counter,register,instruction decoder,ALU and timimg control,RAM and ROM .RTL code and testbench had been written for all the above units.Various stimuli had been given and the logic had been validated. TOOLS USED : simulator : MODEL SIM PE 5.3b. DURATION : JAN-2000 to APR-2000. COMPANY : Vdesign, Pondycherry.
10th Matriculation 1993 -1994 74% Higher Secondary 1994 -1996 81% B E in Electronics and why beauty are good, Communication 1996 -2000 70% (Affiliated to author Madurai Kamaraj University, TamilNadu). Hardware languages : Verilog. ASIC Methodologies : RTL and Behavioural. Assembly languages : Microcontroller. Software languages : C. Operating Systems : Unix,Windows. Script Language : Perl, Unix Shell Scripts, Scheme Scripts(Especially Avanti's Scheme), AWK, SED. Time Conscious. A go-getter. Quest for in romeo, perfection in all assignments. Date of Birth : 02-08-1977.
Language Known : Tamil, English. Nationality : Indian. Marital Status : Single. References : will be provided on request. Three years of strong experience in VLSI/ASIC/FPGA design using Verilog HDL, VHDL, VERA HVL, VI editor, VIM, ModelSim, Xilinx FPGA Foundation series, Turbo C, SignalScan, Advanced Norton Editor, Synopsis DC, Cadence Artist, SPICE, SimG, ADSP2115 toolkit, EPROM/EEPROM programmer under Windows NT/95, UNIX and Sun Solaris environment. Digital Logic Design VLSI/ASIC/FPGA Design ASIC/FPGA Verification EDA Tools Simulation and Synthesis tools Design verification using VERA HVL. Hardware Description Language: VHDL, Verilog Design Tools: Modelsim, VCS, SPICE (TI-SPICE), ADSP 2115 toolkit Verification Tools: VERA Hardware Verification Language (HVL) EDA Tools: Synopsis Design Compiler, Xilinx FPGA Foundation series, Cadence artist Protocols and Standards: Digital wrapper (ITU-T G.709 standard) for FEC in of jekyll 10GWANPHY, SONET OC-3/3c and Single-Gender Essay, OC-192, PCI Bus Interface, ATM, Ethernet, Transition Minimized Differential Signalling (TMDS) for Flat Panel LCD Monitors Languages: C, C++, PERL Operating System: Sun Solaris 2.1, Windows NT/98/95, Unix, MS-DOS Hardware: 10GWANPHY optical board, HUDSON FEC (AMCC S19203), KHATANGA (AMCC S19205), MPC8260. March 2001 - Till date. Digital Wrapper FEC (ITU-T G.709) Optical Channel Overhead Processor FPGA for 10GWAN.
Developed 10GWANPHY (10Gbps WAN) optical board which provided a complete switching fabric solution for Optical Wide Area Networks to support OC-192 Digital wrapper transmission standards (as defined by ITU-T G.709). Developed architecture and coded Transport OverHead (TOH) FPGA which interfaced with HUDSON FEC (AMCC S19203), KHATANGA (AMCC S19205) devices and of jekyll, MPC8260 Motorola Power PC via its Local Bus. HUDSON is fully integrated with Variable Rate Digital Wrapper Frammer/Deframmer, Performance monitor and Forward Error Correction (FEC) device developed by Advanced MicroCircuits Corporation (AMCC). KHATANGA is a dense VLSI device developed by Advanced MicroCircuits Corporation (AMCC) that integrated a 10GbE MAC, a 64B/66B Physical Coding Sublayer (PCS) and a WAN Interface Sublayer (WIS) as baselined by IEEE P802.3ae task force. Used this FPGA to configure HUDSON through its microprocessor interface port, control and monitor status of Optical Channel Overhead bytes/Sonet Overhead bytes (Transport overhead and Section overhead of OC-192c frame) in data channels of water essay HUDSON and to support all Insert/Drop Overhead Channels of HUDSON and KHATANGA.
Defined 16-bit Register Memory Map inside this FPGA with predefined memory locations for author of jekyll, Parallel 8-bit Overhead Insert/Drop channels of HUDSON (both Encoder and Decoder sides) and for serial Insert/drop Channels of Hudson and KHATANGA. MPC8260 wrote overhead byte information into essay examples, FPGA memory locations defined for those particular interfaces, which will later be inserted into author of jekyll and hyde, insert channels on the next frame. On Drop channels FPGA collected Overhead byte information and Essay, stored them in of jekyll and hyde internal predefined memory locations that will be later read by MPC8260. FPGA also monitored all status pins of HUDSON device like Loss of Clock, Out of Frame, Bit Parity Errors (BIP) and reported them to MPC8260. Classrooms! Implemented FPGA on Xilinx Virtex XCV200E series (FG456 package) and implemented all dual port RAMs using 28 Block RAMs available inside this FPGA. Analyzed system requirement specifications and developed architecture for full functionality of the chip.
Automated critical parts of author of jekyll and hyde design verification using VERA HVL. Coded MPC8260 local bus, HUDSON and oocl point, KHATANGA interface modules in and hyde Verilog HDL using VI Improved Editor (Vim). Simulated functionality using ModelSim (Modeltech_5.5). Involved in synthesis of websites modules using Xilinx FPGA tool. Environment: Verilog HDL, VERA HVL, VIM, ModelSim, Xilinx FPGA Foundation series, Windows NT.
Contesse Semiconductor Corporation. October 2000 - February 2001. SONET Transport Overhead Processor FPGA (OHP155) Designed an FPGA as part of GigaStream Switch fabric chipset for collecting and author of jekyll and hyde, transmitting overhead bytes (both Transport overhead and Path overhead of SONET OC-3/3c frame) to/from optical interface. Developed architecture and coding of SONET Over Head Processing (OHP) FPGA interfaced with Spectra155 interface, High Capacity Multi-Vendor Integration Protocol interface (HMVIP) and CPU interface. Apa For Websites! Spectra interface consists of Transport OverHead (TOH) and Path OverHead (POH) interfaces to transmit and receive directions from Spectra chip. Four Optical Switch Processor 155Mbps (OSP155) cards shared a single HMVIP interface in a Time Division manner. Author! The CPU interface is a Network Switching Processor (NSP) CPU interface to OHP FPGA for configuring. TOH/POH overhead byte information collected on HMVIP side is sent to apa for websites corresponding Spectra155 devices.
Similarly overhead data that is sent by Spectra155 device is sent to author and hyde HMVIP interface in why beauty pageants correct time slot at correct frame location. There are eight dual port asynchronous RAMs implemented in this FPGA. Analyzed system requirement specifications and developed architecture for full functionality of chip. Coded transmit side modules of and hyde this architecture in Verilog HDL and tested functionality and performance. Developed self-checking testbenches that automatically generated reactive tests using VERA HVL. Used Xilinx synthesis tool for apa for websites, synthesis of design and generating sdf file. Did post-synthesis simulation of this design. Environment: Verilog HDL, VERA HVL, Modelsim, VIM, Xilinx FPGA Foundation series, Windows NT. Contesse semiconductor Corporation. April 2000 - September 2000. Designed an FPGA to convert Fusion Omni-Connection for Universal Switching (FOCUS) bus interface to Packet on SONET physical interface (POS_PHY) bus interface, so that Vitesse s VSC9112 (OC-48) chip could be interfaced to Vitesse s Network Processor IQ2000 through this FPGA chip.
Designed in Xilinx Virtex-E XCV-300E FPGA. This FPGA had FOCUS 32 bus and POS-PHY-3 bus on either side to convert data (packets) from one bus protocol to other. Of Jekyll And Hyde! Multiple packets can be processed in both transmit and receive directions. Used two FIFOs in examples Ping-Pong mode to carry Fcells in both receiver and transmit side. Of Jekyll And Hyde! Did regression testing of Verilog RTL code. Oocl! Generated random set of valid test cases using a seed value. Used Turbo C for writing a C code, which automatically selected a random number of author and hyde test cases from the valid testcase library using a seed value.
Environment: Turbo C, Verilog HDL ModelSim, SignalScan, VIM, Windows NT. December 1999 - March 2000. Timing Controller Chip with mini-LVDS and FlatLink. Designed a Timing Controller Chip for Thin Film Transistors (TFT) LCD flat panel monitors with MINI-LVDS (Low Voltage Differential Signaling) and Flatlink interface. This chip id designed for customers like IBM, Samsung, LG with programmable display resolutions ranging from XGA to UXGA and to even support SXGA+ and W-UXGA.
Chip interfaces with CPU display card using TMDS (Transition Minimized Differential Signaling) Flatlink standard for digital transmission of Video output data at 1.56Gbps, also it interfaces with LCD drivers through MINILVDS analog interface standard. In Romeo And Juliet! It also generates autogreying patterns automatically to test LCD monitor. Involved in author digital architecture design of chip. Coded the entire architecture in VHDL and did functional testing and simulations of in romeo and juliet code. Author! Used Shell Scripts for taking test bench (testing file used to test functionality of VHDL code).
Used Synopsis DC for 6th grade, synthesis. Performed post-synthesis simulations. Tested and verified actual performance of of jekyll and hyde chip on LG s LCD monitor. Environment: VHDL, ModelSim, Synopsis DC, Advanced Norton Editor, Sun Solaris 2.1. May 1999 - November 1999. Design of Flying Adder Digital Logic for water, PLL (TFP8501) Chip. Designed a Scaler chip for of jekyll, LCD flat panel monitors to support resolutions upto SXGA+/UXGA and to maintain compatibility of various video cards and LCD monitor resolutions by upscaling or downscaling resolutions whenever required. Involved in to point design of Digital logic for Flying Adder PLL (50MHz to 350MHz). Did coding of digital logic in of jekyll and hyde VHDL. 6th Grade! Performed synthesis of design using Synopsis DC. Used SPICE for of jekyll, analysis the analog behaviour of timing critical nets.
Interfaced logic with analog PLL using SPICE. Environment: VHDL, ModelSim, Advanced Norton Editor, Synopsis DC, TI-SPICE, Sun Solaris 2.1. January 1999 - April 1999. Design of essay examples Analog PLL. Involved in the design of a TMDS receiver chip with HDCP for LCD flat panel monitor to support Transition Minimised Data Signaling protocol with High Data Content Protection. Rate of video data transfer on TMDS channel is 1.6Gbps. It enabled data interaction between CPU monitor video card and of jekyll, LCD monitors to be entirely digital. Designed architecture of 6th grade examples Analog PLL (65MHz to 250MHz). Did Analog circuit design of Phase Frequency Detector (PFD), Charge Pump, Bias Generator and VCO.
Used Cadence Artist and author of jekyll and hyde, Spice for analog design. Carried out comic in romeo, all process corner simulations of individual design modules and author, completed closed loop simulations of PLL. Environment: Cadence Artist, SPICE, SimG, Sun Solaris 2.1. October 1998 - December 1998. Power Management Module for TFP401 Chip. Involved in the Design of a TMDS receiver core chip for comic and juliet, LCD monitors.
It supports Transition minimized Data Signaling protocol from and hyde, PC Video cards to LCD monitor. Chip enabled data interaction between PC monitor video card and LCD monitors to be entirely digital. Designed and coded the architecture for Power Management Module in VHDL. Did synthesis of this module. Environment: VHDL, ModelSim, Advanced Norton Editor, Synopsis DC, Sun Solaris 2.1. Mignion Systems Limited. July 1998 - September 1998. Design of comic and juliet Single Phase Energy Meter.
Designed and developed an author Energy Meter architecture using ADSP2115 digital signal processor that calculates voltage, current, power, power factor, frequency and does harmonic analysis. Did assembly language programming of design. Successfully tested design on Single-Gender Classrooms Essay power lines. Environment: VI editor, ADSP2115 toolkit, EPROM/EEPROM Programmer, Windows 95. M. S. in Microelectronics and VLSI Design. ASIC/FPGA Design Verification Engineer. 2.6 years of experience in FPGA Design ASIC Verification. Proficient with coding RTL Behavioral using Verilog and VHDL. Of Jekyll! Proficient with developing test environment for functional verification. Proficient in developing appropriate test vectors using Verilog,VHDL,Vera and e language.
Proficient in writing fully automated test benches. Experience with synthesis and optimization of Verilog/VHDL code Experience with FPGA implementation with Xilinx. Worked on conservation Mentor Graphics Synthesis tool - Leonardo Spectrum, Synplicity Synthesis tool Synplify Worked on different simulator tools- Verilog-XL(Cadence), Modelsim(Modeltech) and VCS(Synopsys). Worked on Mentor Graphics Schematic Entry Tool – Design Architect. Worked on PCI 32 bit @33Mhz Worked with Specman, an ASIC Verification tool from Verisity Familiar with Vera, an ASIC Verification tool from of jekyll and hyde, Synopsys Familiar with DSL Protocol. Familiar with ATM Protocol.
Familiar with AMBA Bus Architecture. Familiar with 8085 and 8086 Architecture. Familiar with 8085 Assembly Language. Familiar with software languages C and Fortran. Single-Gender Classrooms Essay! Good communication skills. ABC Chips Inc, San Jose, California. FPGA Design Verification Engineer. Name of author Project: Network Processor Verification. Wrote test plan for water conservation, one of the modules in the chip. Developed the test bench for the module. Wrote test cases in Verilog.
Developed the different interfaces around the module. This network processor is designed to provide solution for 10 Gb Ethernet, OC-192 applications. Author Of Jekyll! The ingress device supports a POSPHY Level 4 (PL4 ) interface and the egress device supports CSIX interface to a switch fabric. Tools Used : VCS Modelsim. Language Used : Verilog. Name of Project: Link2 Mask Pattern Generation FPGA-SDRAM Controller FPGA.
Designed and why beauty, Synthesized SWATH cycle Controller module. Author And Hyde! RTL coding done in Single-Gender Classrooms Essay Verilog with Verilog-XL and author of jekyll, Synthesized using Synplify Developed the different interfaces around the water conservation, Link 2 FPGA. Author And Hyde! Developed test plan for the functional verification and conservation essay, wrote test cases in Verilog. Of Jekyll! Done the module level verifications and top-level verification. Reported bugs and worked with the design team in fixing the bugs. This module does interface controlling from the essay, input side and takes the processed data to author and hyde and from SDRAM controller. This module also does the essay, interface to the output swath FPGA. This Link2 acts as a link between the input FPGA and SWATH FPGA.
This module does interface controlling from the input side and takes the author of jekyll, processed data to and from SDRAM controller. This module also does the Classrooms, interface to the output swath FPGA. This Link2 acts as a link between the input FPGA and SWATH FPGA. Tools Used : Verilog-XL (Simulator),Synplicity (Synthesis tool). Language Used : Verilog.
Silicon Grafic Systems, Bangalore, INDIA. IC Design Engineer. Name of Project: Rrishti-1-Trace Receiver ASIC Verification. Handled the responsibility of verification of author of jekyll and hyde all NRT transfers using IBM(Internal Bulk Memory) at module level and Single-Gender Essay, device level. Wrote test cases in 'e' language and author, verified them using Modelsim simulator. Reported several bugs in the design and worked with the designers to fix those bugs. The is a trace receiver, which provides the trace recording capabilities for one of the point to point, Emulation controller. The key features of the trace system ASIC are: Provides a maximum of and hyde 4 channels operated at single edge clocking (positive edge, negative edge, positive edge and negative edge, or alternatively 2 channels operated with Bi-phase clocking scheme. Single-Gender Essay! An optional off-chip trace memory of a minimum of 128 M x 32 words provided by an EMIF(External Memory interface) using 64 bit SDRAMS serving all four channels.
On-chip trace static RAM memory organized as 32k x 64 (ie.256 bytes) serving all four channels. This memory is used as channel temporary buffers and scratch memory when SDRAM is used to store channel data. trace packet width from 1 to 20 bits 167 MHz processing rate. The trace peripheral has two distinct sections ,a front end and a back end. The front end (TPFE)acquires the trace data presented by the target and of jekyll, packs this data efficiently into 64-bit words. The Trace peripheral back end (TPBE) dispositions this data to trace memory, managing buffer locations, lengths, and host access to conservation these buffers independent of whether the storing process is of jekyll and hyde, active.
In short, the TPFE contains the relief, acquisition, packing and buffering functions while the author of jekyll, TPBE distributes the TPFE generated data into Trace buffers. Tools Used: Modelsim (Simulator),Specman Elite (ASIC Verification tool). Language used : VHDL (RTL), e language for test cases. Engineering Design Center , Bangalore, INDIA. Hardware Design Engineer. Name of Project : PCI based high speed data acquisition card for signal Processing. Designed the Hardware . Designed the FPGA CPLD . Done the functional simulation synthesis.
Done extensive timing simulation with back annotating the sdf. Done schematic Entry using Mentor Graphics Tool. PCI Add on card with PLX 9080 as PCI Bridge and on the local side uses one FPGA , which does all logic including bus arbitration and data transfer to FIFO . It actually acts as a local processor to PLX 9080. The input to 6th grade examples the card includes 16-bit parallel data stream with strobe and author, 100 Mbps serial streams. Single-Gender! Only one of these may be activated at a given time. The design goal is to accept data rate upto 40MB/s, but the testing will be limited to 20 MB/s transfer to memory. FPGA we were using was Spartan series XCS 40-4 ns.
VHDL entry, compilation and functional simulation is done through Model SIM a front-end tool, then after this we had done synthesis through Leonardo spectrum. From that some edf(edif) files are generated and we open those files in of jekyll and hyde the Xilinx tool. We are using Xilinx tool as the are good, back end. Here we place and route the of jekyll, design and generate timing simulation data. From there one sdf(standard delay format) file is generated. This includes all the internal delays of the device. Why Beauty Pageants Are Good! The Xilinx tool also generates a test bench file. We will apply our stimulus to that Test bench and we make that as the test bench for timing simulation.
So when timing simulation comes we load our design file and the sdf file and simulate. Usually the FPGA has to be configured using a serial EPROM. But in our case since the FPGA is being configured from the system side, it cannot be a permanent data as from EPROM. So we are using the CPLD to author of jekyll and hyde configure the FPGA. Oocl To Point! It will take data through the local bus and load it to the FPGA.
Tools : Modelsim (Simulator),Leonardo Spectrum (Synthesis), Xilinx Design Manager (Place Route). B.Tech Final Year Project done at ER DCI , Tvm, Kerala, INDIA. Project Title: VHDL Model of author of jekyll UART. Developed the architecture Designed and done RTL coding in VHDL. Done the functional simulation, synthesis and comic relief and juliet, mapped to author of jekyll the target PLD. Tool Used : WARP 4.1. Simulator used : NOVA. Host Platform : PC under Win95. Device Mapped : CY7C341 from Cypress ( 192 Macrocell EPLD)
Study in detail one Standard HDL Study in detail about the Single-Gender Classrooms, PLDs Write own HDL code to build a model of of jekyll one Standard UART chip with defined requirements Simulate the code for pageants, functional verification Synthesize and map the design to a suitable PLD. 10.1995 - 05.1999 Degree : c Major in : Electronics and Communication Engineering University :M.G University Kerala, INDIA . Got an award from Silicon Automation Systems ,BANGALORE for being the author, best project team for the quarter of the year 2000 for the Rrishti-1 Project. Got an award from the comic relief in romeo and juliet, customer( Texas Instruments,Bangalore) for outstanding Performance valuable contribution to the verification of author and hyde Rrishti-1. Doing part-time courses in Single-Gender Essay San Jose University for. Course 1- Advanced Logic Design (Winter 2001)
Course2-VLSI Design I (Winter 2001). Course3-Logic Design using HDL- Project- Bluetooth Transmitter. Course4-Logic Synthesis- Done using Synopsys DC. REFERENCES : Can be provided based on author of jekyll request. Seeking a challenging position in VLSI design and/or verification where my skills and experience will greatly enhance the company's success and my personal growth. H/W Description Languages: VHDL, Verilog. Classrooms! Place and of jekyll and hyde, Route: Lucent OFCC (ORCA Foundry Control Center), Altera Quartus, Xilinx Alliance. Synthesis: Exemplar logic (Leonardo Spectrum). Apa For Websites! Simulation: Modelsim, Quicksim from Mentor Graphics, VCS from of jekyll and hyde, Synopsys, VirSim (graphical user interface to VCS for debugging and viewing waveforms). Others: Mentor Graphics DA, Autologic II, Visual HDL, Renoir. Languages: C, C++, perl, Unix Internals like Shell and Awk.
Operating Systems: Solaris 5.6, FreeBSD 2.2.6, Windows NT/98. Networking Protocols: TCP/IP, UDP, ICMP, NIS, NFS, RIP, OSPF Others: PCI. Revision Control: CVS. Saristos Logic Corporation, Mountain View, CA. Consultant, ASIC Engineer. As an ASIC Engineer, was a key individual contributor on a team responsible for conceiving, planning and implementing software and hardware systems required to why beauty pageants validate Storage Area Network (SAN) systems. Storage Area Network (SAN) offers simplified storage management, scalability, flexibility, availability, and author and hyde, improved data access, movement, and backup. Worked closely with the ASIC and hardware development teams with the goal of why beauty are good delivering quality ASIC silicon for advanced storage.
Register/memory access via PCI cycles or PCI DMA transfers or RTL hierarchy. Developed ASIC verification strategies for CSC Custom Logic, CAC Custom Logic, EPIF Data Windows, EPIF Interrupt Controller, DMC Scan Engine, EPIF thrasher Sim that span simulation, hardware emulation (FPGA), and real-silicon environments. Wrote ASIC verification test plans that encompass ASIC block-level, full-chip and SAN sub system-level functionality. Analyzed, designed, developed code, documented, and tested ASIC verification test suites using VCS Synopsys and System c . Migrated test suites developed in the Verilog simulation environment to both hardware emulation and final silicon lab verification environment. Of Jekyll! Each Verification Sim was tested with a model which also takes the same input vectors and generates expected value for that input vectors. The expected Value is checked with the RTL value to verify the functionality of each block. Wrote high level monitors and stimulus models to automate the verification process. Analyzed the timing for Data Windows using Logic Analyzer thus reducing the time for Data Window writes from 1.5 hrs to 18 mins for 1GB of memory on Hardware Emulation Platform. Wrote Scripts for essay examples, HEP (Hardware Emulation Platform) regression suites. Participated in estimating verification development schedules and ensured on author time delivery. Infotech Systems Inc., Boston, MA.
As a Design Engineer was responsible for conceiving, designing, developing and testing digital circuits for both ASIC and FPGA. Designed and tested the why beauty pageants, digital portion of the chip for television. Responsible for author of jekyll and hyde, complete cycle from specification through design and test. Designed the digital circuit using VHDL. Synthesized using Leonardo Spectrum, targeting it to apa for websites Lucent's ORCA series FPGA.
Developed simulations with VHDL and simulated it in Modelsim generating the test vectors for testing the FPGA. And Hyde! Developed Verilog testbenches and tested the circuit back annotating with SDF. Checked the timing of the design generating test vectors for Classrooms Essay, testing the ASIC. Designed and tested Inter-Inter Connect (I2C) circuitry in VHDL and Verilog using Visual HDL. And Hyde! I2C bus defines a serial protocol for passing information between agents on conservation the I2C bus using only a two pin interface. Designed a I2C bus slave interface controller using Visual HDL. Synthesized the circuit using Leonardo Spectrum and targeted to Lucent's ORCA series FPGA. Developed test benches in VHDL for testing the proper working of the author and hyde, design using Modelsim. Designed and tested the read channel chip. Worked on three different versions of the read channel. Comic In Romeo! Designed the of jekyll, FPGA using Visual HDL generating the RTL for the design.
Tested the design writing VHDL test benches for the proper operation Placed and routed the design using ORCA Foundry Control Center targeting to the Lucent's ORCA series FPGA. Evaluated place and relief, route tools for the read channel chip. Of Jekyll! Evaluated the design to test the read channel chip with various FPGA place and route tools. Water Conservation Essay! Tools evaluated include Xilinx's Alliance, Altera's Quartus tool and Lucent's ORCA Foundry Control Center. Designed and tested the Test Access Port (TAP) controller using Visual HDL.
Designed an IEEE standard TAP controller. Generated VHDL code from author of jekyll, Visual HDL and tested the controller by writing test bench in VHDL. Simulated it using Modelsim. Water Essay! Developed Perl script for conversion of Spice netlist in to VERILOG netlist. And Hyde! The script written in perl takes in a Spice netlist and gives the Verilog netlist. Point! Developed testbenches for the Verilog netlist for the million-gate chip. Developed test sequence for this verilog file for checking the operation of the chip.
Master of Science, Electrical and Computer Engineering, Southern Illinois University Edwardsville, January 2000. Relevant course work includes Digital VLSI Design, Digital Computer Architecture, High Performance Architecture, Analog VLSI Design, TCP/IP Inter Networking, C++ Programming. Structural and Behavioral RTL description of a Simple Educational 16 bits Processor in Verilog. The structural description of the of jekyll, data unit, the control unit, SRAM and other modules were coded and tested. Other Projects Design of a Linear Interpolation Filter using Verilog and websites, full custom IC layout. Design of a Simple Educational Processor using VHDL. Designed and simulated a sigmadelta modulator for an EEG IC. Bachelor of and hyde Engineering, Electrical and Electronics Engineering, University of Madras, May 1998. Reference: Furnished upon request. ASIC-FPGA Design Verification Engineer.
To work where I am given the opportunity to apa for websites assionately exploit my knowledge to the fullest level of satisfaction both personally as well as for the company I serve on author the whole. SUMMARY OF EXPERIENCE: Over 7+ years of experience 5+ years of relief experience in Hardware Design, Development Verification using ASIC, PLD, CPLD FPGA Designing Verification, Board simulation, ANSI C, Assembly, C++, PLI, PCI, VLSI, PCB, Verilog, Synopsis, VHDL,VERA, Gigabit Ethernet,(Networking) SONET,ATM, Device Drivers , Win Board, Synthesis, Verification of Design.CMOS,Embedded System (SOC),Real Time Operating System RTOS), VxWorks, Logic Analyzer, Simulator, Emulator Programming of RAM(SRAM DRAM) With excellent analytical and and hyde, programming skills. Very conversant in documentation, presenting prototypes, client interaction, quality assurance. Good communication and 6th grade essay, interpersonal skills. Strong Points include quicker grasp to new concepts, the ability to pursue matters in of jekyll great detail and able to work in a team. Bachelor of Electrical Engineering from Bangalore University. Jan 2000 - Present DSSABC Software, Inc., CA, USA.
Feb 1998 - Nov 1999 FDD Containers Limited, London, UK. Oct 1996 - Jan 1998 RANDY ENGINEERING, Tripoli, Libya. Jul 1994 - Sep 1996 Advanced Systems Solutions, Delhi, India. Client: Smart Networks Utilties, Santa Clara, CA Aug 2000 to conservation Present. Scope of the project was to design develop a micro controller chip for networking purpose on networking boards, which sends and receives data digitally Supports Gigabit Ethernet on Fiber Optics. My Role: As a team member I was involved in.
FPGA ASIC design Wrote verilog HDL code for design. Author! Wrote test bench for verification in comic in romeo and juliet C Used PLI for communication with Verilog. Integration testing verification. Functional testing verification. Environment: Verilog HDL , Xilinx-4000 Series , Win Board , C , PLI , ATM, VxWorks , Synopsys. Client: Digital Design, Santa Clara, CA Jan 2000 to Aug 2000.
The objective of this project was to design, developed the data networking boards and test benches for of jekyll and hyde, verification purpose of pre written functions in verilog . Simulation and water conservation essay, hardware development of author communication subsystems using the sections reconfigurable-prototyping. Design, simulate, and test digital hardware. Developed data networking boards, and backplanes. Why Beauty Pageants! Performed the author and hyde, design, capture the schematics and essay, oversee the board layout. Performed board simulation and signal integrity. Environment: Verilog HDL , Xilinx-4000 Series ,VERA, Win Board , C , PLI , VxWorks. FDD Containers Limited, London, UK [Feb 1998 - Nov 1999] Project: DSP Motion Controller 09/98 to 11/99.
Client: FDD Container (UK) The purpose of the project was to design and develop micro controller chip 80188EB for controlling the motion of Mechanical Equipment Boomer there was servo motors which controls Boomer Motion.Servo Motor was controlled by the tech called DSP motioncontroll (Digital Signal Processing). The RTOS was designed implemented on author higher priority algorithm, the signals of higher priority is served earlier than a signal with lower priority. Oocl Point! The code was written in author and hyde c inline Assembly on relief in romeo and juliet Host Computer. Design, simulate, and test. Programming of SRAM DRAM. Writing Test Benches for author and hyde, Verification in verilog C. Performed board simulation. Environment: C, ASIC, Test Bench for Verification, Perl, Synthesis, Verilog, Inline Assembly, Target 80188EB,RTOS VxWorks. Water Conservation! Device Programmer, Host Computer IBM PC, Simulator, Emulator, Logic Analyzer.
Project: Micro controller Development (Embedded System) For Geo Systems 02/97 to 09/98. The purpose of the project was to design and develop micro controller chip 8051EB for controlling heat Generation in Turbines of thermo electric Power plant. Of Jekyll! The processor controls the steam temperature. 6th Grade! Which receives the signals from of jekyll and hyde, Boiler sensors. If due to any reason the temperature goes below specified level the alarm will be activated. It had the provision of printing the Time versus heat graph controlled by the processor 24/7.Programming of the RAM was done by c inline assembly. Device programmer was used to copy the relief, image files on of jekyll the chip. Design, simulate, and apa for websites, test micro controller chip. Of Jekyll And Hyde! Programmed SRAM DRAM. 6th Grade Examples! Wrote verification code in verilog C Performed the design, capture the schematics and oversee the board layout. Performed board simulation.
Environment: ASIC Design, VHDL, Verification, Test Bench, C, PLI, Inline Assembly, Perl, Target 8051, RTOS PSOS, Device Programmer, Host Computer IBM PC, Simulator, Emulator, Logic Analyzer. RANDY ENGINEERING Tripoli, Libya [Oct 96 - Jan 97] Project: Material Management System 10/96 to 01/97. DOS based Stand alone Database Application developed under C++ for Civil Engineers providing Menu Driven User Interface for calculating the Quantities of author and hyde material required and its Costing, providing an easy access to feed the User input data. Water Essay! Its related Quantity and author, Cost will be calculated automatically with the help of in-build functions related data Information that is also capable of modifying as per the user specifications and pageants are good, standards.
It takes the Complete Details of a building (to be constructed) by providing an of jekyll Interface and Calculates the quantity of material required with its estimated cost, as per the standards specified. It provides an easy access for 6th grade essay, modifications. Environment: C, UNIX and MS DOS. Smart Systems Solutions, Delhi, India [Jul 1994 - Sep 1996] Project: Employee Scheduler Management Jan 96 - Sep 96. A standalone Application developed using Visual C++ 5.0, for Microsoft Windows95 and Microsoft Windows NT, to be used as the of jekyll, Employees Schedule and its Related Information, in a Large Companies, Hospitals etc.
Developed system allows you to get detailed Information with Graphical Representation related to an employee and its Schedule (Working and Leave Duration's Designed for a Complete year) Allows Online Modifications for Updating the Individual Schedule of an employee, and 6th grade essay, its related information. Which intern Automatically updates the related Schedules of other employees if desired. Environment: Visual C++, MS Windows 95. Project: Management and Security of File System Feb 95 - Jan 96. An Application Program of which the author of jekyll and hyde, Core Part is handled using C++, and the GUI (Graphical User Interface) is handled using Visual C++ for are good, Microsoft Windows 95 and author of jekyll, Microsoft Windows NT.
Which allows the user to maintain its File System with Security, providing File and oocl point to point, Application Locking. With which it is possible to lock any Executable Program from being unauthorized Access, by providing Password facility. It is author, Capable of Locking Windows95 from being Loaded Unauthorized at the Boot time. Provides an Easy and Quick File Search. Provides Quick Access to file Opening and Single-Gender Classrooms Essay, Executing. Provides File Viewing facility before editing the files, giving an Easy access to Editing. Environment: Turbo C++ 3.0, Visual C++ 5.0, and MS Windows 95. Project: Standard Product Impress Jul 94 - Feb 95. Impress is a standard integrated package targeted at the Printing and Advertising Companies as the major customers. It was designed and developed by Thomson Technologies, India. Author Of Jekyll And Hyde! The product included modules such as Financial Accounting, Purchase, Sales, Inventory and Production (Studio Section Camera Section).
Was a member of the team, which designed the system? Other responsibilities included coding and apa for websites, testing. Developed 12 forms and various other Reports. Environment: Visual C++, Visual Basic, MS Windows 3.1. Visa Status : H1B. References: Available on request. Nine and a half years of strong experience in Verification of ASICs using Verilog, VHDL, VERA, Verilog -XL, Synopsis VCS, Mentor Graphics Co-Verification Environment, Assembly Language on Unix platform.
Expertise in writing Verilog Model, developing test plans, Quick test writing and of jekyll, setting up Verification environment in Verilog/VHDL. Good knowledge of PCI protocol. Hardware Description Languages: Verilog, VHDL High Level Verification Language: Synopsis VERA CVE: Mentor Graphics Co-Verification Environment Simulation Tools: Verilog-XL, Synopsis VCS, Veriwell Languages: Assembly Language for Intel MCS 51/Motorola MC68000/MIPS processor/ ASM 51 Assembler and Linker/in circuit emulator 51, C OS: Sun Solaris, Unix, Windows 95/NT. LSX Technology, Inc., Moutain View, CA. August 01 till date.
Verification of PCI bridge( PCI to local) PCI 9656. Wrote random tests for the verification of the PCI 9656 for Direct Slave . Direct Slave means that the chip is the slave on the PCI bus, Direct master means that the chip is the master on the PCI bus. Worked on Single-Gender Essay PCI compliance testing for the PCI 9656 using Synopsys PCI compliance suite. Worked on FIFO testing. Of Jekyll And Hyde! There were 2 FIFOs. One for the Direct slave read and Single-Gender Classrooms Essay, the other for the direct slave write. Wrote various test and of jekyll, verified the functionality of the FIFOs for in romeo, both the of jekyll and hyde, empty and full condition. There were numerous condition to fill and empty the comic relief, FIFO. Author! One such condition could be no grant on the local side or on the PCI bus for the external master. The chip has 3 modes namely M, C and J modes . Apa For! These modes are the local bus types. M mode is author of jekyll and hyde, 32 bit address/32 bit data, non multiplexed direct connect interface to to point MPC850 or MPC860.
C mode is 32bit address /32 bit data non multiplexed for intel processor i960 and J mode is and hyde, 32 bit address/32 bit data multiplexed. Environment: Verilog, Sun Solaris. Visitor Graphics Corporation, CA. January 01 - till date. Field Application Engineer. Was responsible to give product presentation, demonstration for the Seamless CVE (Co- Verification Environment). The Hardware and water essay, Software Co- Verification helped in software debugging, shirk the system integration time and avoid prototype respin. And Hyde! Was required to and juliet perform evaluation of the product at the customer site.
Satisfied the customer about the utility of the product through a question/answer session and with follow up visits to of jekyll and hyde potential customers. Websites! Performed evaluation of the product and against the product of competitors. Environment: Verilog, CVE, Assembly, Sun Solaris 2.x. Advanced Networks, CA. December 99 - December 00. Verification of a Packet Classification ASIC. The ASIC was used to offload the network processor of the job of classification of the packet. The packets could be classified on the basis of the header or any byte of the data payload. The ASIC had system bus interface, ERAM interface, AOC PIB modules. The interface of the chip was like memory so supported both zbt and non zbt modes. The system bus could be configured as 64 bit or 32 bits.
The speed of the ASIC was in the range of 50 - 100 MHz. Wrote diagnostics to verify the author of jekyll, system bus interface using Verilog. 6th Grade Examples! Build the author of jekyll, Chip Verification Environment using VERA. Debugged the failing test cases. Found several bugs and fixed the bugs.
Environment: Verilog, VERA, VCS, Sun Solaris 2.x. June 99 - November 99. Verification of a Networking SOC. Involved in Verification of a Networking SOC having MIPS Processor, SDRAM Memory, MAC, PCI and essay, HDLC. Was responsible for Verification of the bridge between the author and hyde, MIPS Processor and the Toshiba Proprietary bus using Assembly and Verilog in a multi master System Verification environment. Developed several MIPS Assembly and Verilog based test to verify the functionality of the G bridge and water essay, HDLC.
Translated the unit level test cases for HDLC to system level tests. Verified the tests at full chip level. Found bugs, notified the designer and suggested fixes. Environment: Verilog, Assembly, VCS, Unix. January 99 - May 99. Verification of a Network Output Controller. Network Output Controller was responsible for and hyde, moving data (packet) from the packet buffer (external SRAM memory) through the essay, port FIFO s to the network interface. Verified the above functionality of the and hyde, NOC by writing the functional models in websites Verilog. And Hyde! Verified functional models.
Verified Packet buffer read and writing. Packet buffer was read and written as 1024 bits at point to point a time in author of jekyll and hyde 11 clock cycles. Verified the packet Queue (PQ) which performed queuing and 6th grade examples, dequeuing of the author of jekyll, packet through the Single-Gender Classrooms, star address in PB and the skip over mask. Verified Packet Receiver which received packets from all the 50 ports at the network interface in the TDM manner. Functional model of the author of jekyll and hyde, NOC was written before the water essay, RTL could be plugged with other functional models.
RTL replaced the NOC model. Developed the test bench and author of jekyll, wrote task for water conservation essay, specific functionality. Developed test plans, test cases for the Chip Level Verification of the ASIC using Verilog. Found and fixed bugs. Environment: Verilog, Verilog -XL, Sun Solaris 2.x. March 98 - December 98. Design and Verification of HDLC Controller (Project Lead)
Involved in Design and Verification of of jekyll and hyde HDLC Controller with a generic 8- bit microprocessor interface. The HDLC controller framed according to the HDLC protocol. The frame checksum generator and checker were implemented. The controller was to the ITU Q 921 specification. Designed the HDLC controller. Involved in portioning of the design into Transmitter and Receiver. Verified the HDLC. Synthesized the apa for, HDLC. Environment: Verilog, Verilog-XL, Sun Solaris 2.x. Sonet Technologies Pvt Limited. January 97 - February 98.
Development of VITAL ASIC Libraries. Verilog to VITAL converter was used to translate the Verilog Structural Model to VITAL. Testing was done on Quick HDL simulator, which was one of the sign off simulator for LSI logic. Was responsible for Conversion and Simulation. Environment: VHDL, Quick HDL, Unix.
Sonet Technologies Pvt Ltd. April 95 - December 96. Development of Test Bench for BUS Interface Model for of jekyll, MC68030 and water conservation essay, MC68020. This was implemented using the Co- Verification Environment developed by author and hyde Mentor Graphics. Water Conservation Essay! The hardware (Verilog/VHDL) was simulated on HDL simulator like QuickHDL and the software was simulated on author the software simulator (different for each processor). The Bus Interface Model was specific to the processor and 6th grade, generated bus related cycles for and hyde, the processor depending on the type of access. The tool was used in designing embedded system where the software could be verified against websites, the hardware before the hardware prototype was made. Environment: Verilog, VHDL, CVE for Mentor Graphics, Unix. Parametric Network Limited.
November 91 - March 95. Development and Verification of a Keyboard Controller using 87C51FA Microcontroller. Developed assembly language programs. And Hyde! The keyboard and the system (486 PC) serial communication was established and keys were scanned. Whenever any key was pressed, the apa for, make and the break key codes were sent serially in an 11-bit format to the system (486 PC). Of Jekyll And Hyde! Provision was made for interfacing more than 1 keyboard with this keyboard controller. This also included the standard PC keyboard. Environment: Assembly, Unix. To work in ASIC DESIGN/VERIFICATION - Verilog/VHDL modeling, logic synthesis, logic verification, place route, FPGA and CHIP layout. VLSI Logic design - Complete design flow from comic relief in romeo, RTL to layout. Excellent in both VERILOG VHDL Proficient with Ethernet (MAC), ATM Utopia Level I II protocols.
Complete understanding in architectures of PCI OHCI. Proficient with USB. Knowledge in Unix, Perl and 'C'. Knowledge in VERILOG PLI CONCEPTS. Good experience in Digital synthesis and Place Route. Configuring CPLD with bit blaster using MAX+plus II. Author! Expertise in Altera /APEX FPGA. Experience in water essay Assembly Language. Analyzed circuits using SPICE. Simulation : Verilog XL from Cadence 2.3, Model TECH 5_3pa version (VHDL Verilog), Leapfrog Simulation for VHDL Accolade Peak VHDL tools.
Synthesis : Leonardo synthesis tool from Exemplar, Synplify from Synplicity. P R : Altera MAX+plusII , Lucent , Quarters Tool for APEX Devices. Renoir Tool and Xilinx Foundation series 2.1I from Mentor Graphics. Others : Signal Scan and De-bussy for waveform generations Assembly Language : Programming Logic works, C, PERL,UNIX SPICE, MAGIC IRSIM. Author And Hyde! 'C' Compiler : Green Hills Software. Company I : Analog Systems, CA. Duration : Jan '00 - Till Date. Designation : Member Of Technical Staff. Company II : Trenton Chip Devices, Inc., CA. Duration : May '99 - Dec '99. Designation : VLSI Design Engineer. Company III : Trenton Chip Devices, India.
Duration : May '97 - Apr '99. Designation : VLSI Design Engineer. Company : Analog Systems , Inc. Location : Santa Monica, CA. Designation : Member Of Technical Staff. Project : AD 6489 Voice Over Packet Solution, Fully Integrated VoP Solution. Duration : August 2000 - Till Date.
The Si was taped out on Oct '2001. Oocl! The Total No. of gates is 1.2 Millions. It operates on 125 MHz. It's a .18 micron technology. Of Jekyll! The AD6489 family of packet processors performs voice and pageants are good, data packet processing for the SOHO (Small Office/Home Office). SME (Small Medium Enterprises and RG (Residential Gateway ) Market. The features it supports is Layer 3 + Software, Voice and Fax, Signaling, Networking Management, Security, Physical Interface, ATM Support, AAL5, IMA, FR and PPP and of jekyll, Memory support. The AD6489 solution helps the system vendor go to market faster by providing a highly -integrated SoC. Water Conservation Essay! The SoC comes with a reference board and complete software solution for both VoIP VoATM based solution. A Powerful Application (API) and plenty of processing power are available for the system vendor to provide differentiated value addition to the system.
It is having 3 processors namely Control Processor Engine, Wan Processor Engine Security Processor Engine. The AHB bus being the major interface between these processor and the Peripherals, which includes like (UTOPIA, HDLC, UART, GPIO, USB, SPI). There is an and hyde intelligent DMA, which does the memory transactions between memory and the processors. Then for apa for websites, the WAN interface we have 10/100 EMAC and also supports external PCI USB. Author Of Jekyll And Hyde! It has on Single-Gender chip SDRAM controller flash controller 200KB of on-chip memory for voice and data processing. Developed Designed in verilog the intelligent DMA block. Author! Which does all the major operation for the above chip AD 6489 the pageants are good, rams. Created Testbenchs for of jekyll and hyde, the blocks like UART, SPI DMA.
Developed the verification methods created testcases both normal corner for UART, SPI DMA. Relief! Did the RTL netlist simulation for UART, SPI, DMA. Did the other testing like JTAG, MBIST, EMAC, PCI, USB Testing on the RTL netlist level simulations. Did the random testing for the above blocks at of jekyll the system levels and also for the other blocks. Verilog XL from Cadence 2.37 Signal Scan/De-bussy for waveforms. Duration : Feb' 00 - July '00. Designed, developed verified the UMAC in VERILOG. This s going to water be used and cable modem chip. The design was target for APEX FPGA from of jekyll and hyde, altera 20K200. The design basically consists of 5 interfaces. Physical, Data Drain, Encryption engine, Data Fill and Microprocessor modules.
The PHY interface can get the data from simultaneously from 8 devices and gives to 6th grade examples Data Fill interface via data FIFO. It also stores the relative information in another FIFO called pointer. From these FIFO Data fill interface dumps the data to author of jekyll the memory . The data drain gets from memory and gives to the microprocessor module. The design operates in 3 different frequencies. The input data is coming at 10Mhz, which is to the phy interface. The microprocessor interface is working on 60 Mhz and the rest of the interface is working on 40Mhz.
Verilog XL from Cadence 2.37 Signal Scan/De-bussy for waveforms. Max-Plus II for P R. Synthesis by Syniplify from synplicity. Duration : Jan '00. Implemented the SPI interface in VHDL between SPI and external BUS interface used for IMA. Leapfrog Simulation for VHDL. Company : Trenton Chip Devices , Inc.
Location : Sacramento, CA. Designation : VLSI Design Engineer. Project : Transceiver Subsystem. Duration : Nov'99 - Dec '99. Designed Developed controller for DPRAM (in verilog) which is essay, used get the author, Data from ATM fpga and essay examples, feed to the microprocessor. Of Jekyll! The microprocessor reads the data from dpram which was written by the ATM fpga. Designed the code in Verilog. Compiled and simulated in MTI Verilog simulator (Model Tech).
Renoir Tool and Xilinx Foundation series 2.1I from Mentor Graphics. Project : Internet Data Storage. Duration : Aug'99 - Oct'99. To store the Data into the Disk Array through the are good, user in the internet.The block gets the data to author and hyde be written into and juliet, the disk module from the author of jekyll and hyde, memory for which the CPU provides the address. The data with the Single-Gender Classrooms Essay, parity is then stored in author and hyde the memory. Apa For Websites! While reading the data, it regenerates the parity and checks with the parity that is read. On error, the date is invalidated. The parity and data are stored in the memory through the interface. DMA is used for reading and writing the data into the memory for burst of transaction. Developed Designed the of jekyll, logic in verilog which is specific to Disk Module and it provides the following functions:
Raid Parity generation Raid Parity verification Raid Parity reconstruction Interface to the Main Memory DMA. Compiled and 6th grade essay examples, simulated in MTI Verilog simulator (Model Tech). Duration : May'99 - July'99. The OC3 FPGA communicates using either ATM Cells or POS. In ATM mode, the data path is between the SAR and the PHY via the UTOPIA slave level 1 to UTOPIA master level 2 interfaces. Utopia1 slave is running on 25 Mhz and data rate is 53 bytes.
UTOPIA 2 master is running on 33 Mhz and date rate is 64 bytes. There are two downstream FIFOs and two upstream FIFOs. The FIFOs are used in ping-pong mode alternating FIFOs between ATM cells. Author Of Jekyll And Hyde! No parity or packet error reporting of any kind is supported. Synthesized the OC3_FPGA, which had the modules like Lucent PCI Master and Target. Module ware Utopia Master and Slave. Interface Data Path Between Tetra and SAR.
Completed Place and Route of the above project which was mapped with the Orca Foundary Family, of the pageants, Architecture 3T800 Series. Totaled to author and hyde 390 numbers of PFU. Synplify Syntheses Tool From Synplicity V 5.1.4. Lucent Place And Route Tool Version 9.35. Company : Trenton Chip Devices. Location : Chennai, India. Designation : VLSI Design Engineer. Project : Verification Of USB Open Host Controller. Duration : Jan' 99 - Apr'99.
Member in the verification of Open Host Controller, which controls the transaction running on USB bus. It fetches the Endpoint Descriptor and Transfer Descriptor from essay examples, memory and performs the appropriate action depends on the information from the Descriptor. These Descriptor includes the author of jekyll, information about the device. Developed the PCI Test Bench for why beauty pageants, OHCI. Created testcases for the functional verification of OHCI. Host Controller is a device which serves devices attached to the USB bus. It is interfaced to the PCI bus for accessing the author of jekyll, system memory. Designed this core using both VHDL and pageants, VERILOG.
This design has different types of author modules. 6th Grade Essay Examples! PCI Master and Target block Open Host Controller block Interface between USB and PCI side Host SIE Root Hub. Project : Design of PCI master/target. Duration : July' 98 - Dec' 98. Designed OHCI compliant PCI master/target function. Done testing on this module. Carried out synthesis of all these modules using EXEMPLAR LEONARDO. Done Place and Route using ALTERA MAX+plusII. PCI Master initiates transaction on of jekyll the PCI bus for getting the ED/TD's or data's for USB devices from main memory or updating the data from USB devices to main memory. PCI target responds to websites configuration transaction's and other Bus Master's initiates transaction. Implemented the logic for PCI Target and PCI Master.
Tested the whole project using ModelTech simulator. Synthesized the logic using Exemplar's Leonardo tool. Author! Max+plus II tool is water essay, used for Place and Route. Mapped the PCI core into the Altera Flex10k30 device. Mapped the USB side core into author, the Altera Flex10k100A device. Mapping the whole design into ASIC Library and testing is in websites progress. Total gate count for OHCI project is 33,000 gates. Project : Design and author of jekyll and hyde, verification of Hearsee-USB Logic.
Duration : Jan'98 Jun'98. Hearsee is a video compression chip used to oocl to point capture active video pixels from the digital camera, scales down to 2:1/4:1 ratio, compress the and hyde, pixels and deliver the encoded data to are good the computer through USB. It consists of video camera interface, scalar, a high quality compressor and USB interface. The picture information coming from the camera is processed by the hearsee block. Of Jekyll And Hyde! This data is first scaled down by scalar block according to the mode of operation. This scaled down data is apa for websites, compressed by the compressor block. This compressed form of data is sent through the USB cable. Designed the data flow for author and hyde, the still video capture mode of Hearse Created testcases for the functional verification of Hearsee individually in why beauty pageants still, motion capture modes as well as combination of still-live modes Performed simulation in modeltech VHDL simulator. Project : Verification of USB Device Core. Duration : Nov' 97 - Dec' 97. Involved in of jekyll and hyde the verification of apa for a USB Device Core.
Project : Design of FIFO. Duration : Oct' 97. Designed a 8-bit 256 deep FIFO with revert and latch read pointers. Used Model Tech VHDL/Verilog Simulators and Leonardo Synthesis Tool. Target technology was Altera FLEX10K device. Project : Design of a bit stuffer. Designed the bit stuffer in logic works, using VHDL and Verilog. Project : Design of a Traffic Light Controller and Stepper Motor. Duration : Aug' 97. Written an Assembly Language Programme for Traffic light Control and Stepper Motor Controller.
Used the add-on card with 8253 Timer and PPI chips along with 8379 for author of jekyll, testing of this design. Bachelor of Engineering (Electronics and Communication) 1997. Madras University, INDIA. 7.5 GPA. REFERENCE : Available Upon Request. 1200 Moonlight Dr. Santa Clara, CA 95127. Valid H1-B till 2004. Domain Skills: Micro controller and Microprocessor design and verification.
Understanding of 6th grade essay examples communication Protocols. Applications: Digital Design Methodology Network Flow, RTL coding, Synthesis, Simulation of author full chip and block level designs. Functional verification of full chip design, Physical design skills at 6th grade chip level, Physical Verification, Writing Software utilities Languages: PERL and of jekyll, Shell Script, C, HTML CAE Tools: Verilog-XL, NCVERILOG, Polaris, Synopsys Synthesis tools, Cadence Composer, Compass tools, DRACULA for physical verification, TransEDA and HDLScore for code coverage, AVANTI tools. OS: UNIX, SUN-OS, and WINDOWS. Network Alliance Corporation. Verification Of a Re-configurable Network Processor (09/01 - present)
Client: Crystal Systems, Santa Clara, CA. Crystal's CS2200 is a re-configurable processor with embedded ARC core mainly targeted at Single-Gender Classrooms the networking applications. Responsibilities require me to write directed tests to verify the tile block and author of jekyll, random tests to verify concurrency. Code Coverage Analysis (07/01 - 08/01) Client: Vertex Networks, Santa Clara, CA. My role required me to analyze the test vectors from the viewpoint of code coverage, and furnish suggestions to the verification team as per water conservation essay the findings. Verification Of a Re-configurable Network Processor (02/01 - 07/01) Client: Crystal Systems, Santa Clara, CA.
Crystal's CS2200 is author and hyde, a re-configurable processor with embedded ARC core mainly targeted at the networking applications. Responsibilities required me to write tests to verify the various modules of the chip, e.g. Water! fabric, road-runner bus, code generator. Of Jekyll And Hyde! I also did the code coverage analysis to optimize the test suit for pageants are good, better fault grading. Teriola India Ltd., Gurgaon, India. VLSI Design Engineer. Design Of a CAN protocol implementation (11/00 - 01/01) The Control Area Network (CAN) protocol is author of jekyll, used in automobiles for oocl point, communicating between various controllers inside the vehicle. The project involved converting the latch based design to a flip-flop based design. This process involved major timing issues as latch based design had a lot of cycle-stealing.
Responsibilities required me to and hyde convert the RTL to point to point flip-flop based design and simulate the design to see there are no issues with the conversion. Author! Finished my part in record time. Design Of a microcontroller (10/99 - 10/00) The micro-controller is to be used in automotive Industry for websites, anti-skid braking. It is based on Motorola's Mcore processors. Responsibilities required me to verify, Synthesize and PR the Timer block. Author! This project involved the point to point, full Network design cycle, except for author of jekyll, RTL Coding. MARCUS Tech, Bangalore, India. VLSI Design Engineer. Design Of a 16 Bit RISC Processor (08/99 - 09/99) It is a general-purpose 16-bit microprocessor core, designed to be used in DSP engines.
The project involved full chip design using Design Reuse methodology.Responsibilities required me to apa for websites design, verify and synthesize the of jekyll and hyde, Program Counter block. Functional Verification of Essay a 16 Bit RISC Processor (02/99 - 07/99) ARC85 is author and hyde, a family of general-purpose 16-bit microprocessor cores, primarily designed for embedded applications. The project involves the Full Chip functional Verification of the microprocessor core. The chip was verified using Compass-generated vectors. Comic And Juliet! I was responsible for writing the test-bench for the full chip simulation.
Later, the and hyde, Compass-generated vectors were used to generate the Verilog format vectors for full chip testing. The work also involved the pageants, testing of vectors on the netlist generated by the Synthesis tool. Netlist to RTL conversion was also part of the project. Redesign of 8-bit Microcontrollers(SPC700 series) for Sony Corp(04/98 - 02/99) SPC700 series is a general-purpose programmable 8-bit microcontrollers originally designed by and hyde SONY. The project involved the redesign of the whole series from 1.4 Micron technology to to point 0.7 micron tech. It also involved dynamic to static logic conversion. Of Jekyll! Participated as a member of a 3 member team.
Redesigned 2 of pageants a series of author 4 microcontrollers. The redesigning involved Logic Conversion, Schematic Entry, PNR and Functional Verification at the block level as well as the websites, full chip level. Author Of Jekyll And Hyde! Played major role in oocl point to point setting up the test environment for the full chip. Of Jekyll! Executed the project successfully in oocl point the first go. Developed a software utility, indigenously, using Perl Shell scripts to convert the stimulus file from ANDO-DIC 8031/32 format to a Verilog compatible format. Of Jekyll And Hyde! This saved a lot of expense to the company. Granada Consultancy Services. Assistant System Analyst. American Express Milleniax Conversion (10/97 - 03/98) The project involved the why beauty pageants, modification of the existing code for American Express to make it Y2K compliant. The project was divided in author of jekyll various implementation Groups (IG's).
Each IG was responsible for modifying and testing a market. Participated as a member of a 4 member team and later as an Implementation Group leader. Training in Software Development Process (07/97 - 09/97) It involved training on different Software Platforms, Programming Languages and to point, Graphical User Interface. It also consisted training on Software Development Methodologies. It also involved a project in C on UNIX to manage an employee database. Advanced Chip Synthesis Workshop (2000) The workshop was conducted by author and hyde Synopsys Inc. at Teriola, Gurgaon. Single-Gender Classrooms! It focused on advanced chip synthesis methods.
1997 B.Tech. in Electronics Communication Engg (DGPA 8.28) IT, BHU, Banaras, INDIA. Project : Implementation Of Star LAN using PC-AT (11/96 - 04/97) The project involved implementation of Star-LAN using PC_AT's to connect two labs in Electronics Department of IT,BHU. The process involved PCB design and C coding of device driver for the LAN card. Sr.chip designer, with MSEE in VLSI, from Nortel Networks, experienced in ASIC, FPGA, HDL, C/C++, ATM, IP 10GE, SONET and author and hyde, RT embedded, applies for ASIC / FPGA design or H/W position. MSEE in VLSI Design, ECE of UNB, New Brunswick, Canada. Ph.D.
Candidate in Computer-Aided Design Center, China. MSCE in Computer Engineering, WU, China. BSEE in Electrical Engineering, WU, China. SUMMARY OF QUALIFICATIONS. Skilled in all phases of Front-end ASIC, FPGA design, including architecture development, writing specification, partitioning, RTL coding, function simulation, synthesis, timing analysis. Skilled in Verilog, VHDL and SystemC, Specman, Vera, C/C++ and tools: Synopsys's DC, Primetime, GNU, VCS, Verilog-XL, NCverilog, Modelsim, SignalScan and Synplify, Xilinx. Skilled in board level hardware design, Schematic, Simulation, and PCB in 6th grade OrCAD, Viewlogic. Author And Hyde! Rich experience in H/W and 6th grade essay, S/W co-design for MPU-based embedded application systems. In-depth working knowledge of ATM, IP, MPLS, GE, SONET and related network protocols, and VLSI devices and author of jekyll and hyde, theory, ASIC design, CPU architecture, PCI, DSP and firmware development. Good experience in firmware programming in C/C++ under PC DOS, VxWorks and QNX OS.
Some experience in mixed signal CMOS IC circuits design, simulation, layout by websites Cadence tools. Excited by and hyde the challenge. A team work player with creative, self-motivated, cooperative spirit. I have worked in Single-Gender Classrooms 6 companies and universities in Canada and China in the positions of Senior ASIC Design Engineer, ASIC / FPGA Designer, Lead Hardware Engineer, Hardware Engineer, Firmware Programmer and Research Assistants since I graduated as a MS in Computer Engineering in author and hyde 1988. These positions carry over 4-year real experience in ASIC/FPGA/VLSI design, and over apa for websites, 6-year real experience in system and hardware board level development, and 10-year systematic theory studies. My background covers Electronics, Microcomputer, Network, Communication, and Control system.
Following are my some ASIC/FPGA hardware and system design experience in real world in order: Vegatron Networks, Toronto, Canada. 2001 Oct 1 - present. Senior ASIC Designer, SoC Architecture Engineer. (Permanent full-time) Development of a System-on-Chip ASIC for a new high-performance switching Router. SystemC, C++, GNU/Visual C++ 6.0, Scripts, High Speed I/O, Verilog, DC, PT, VCS, IP protocols. Developing a high-performance IP routing architecture and interconnection protocol for the 4-million gates ASIC based on multiple IP cores. Writing a detailed ASIC design specification for RTL design.
Vermax Networks, Ottawa, Canada. May 2001 - Sept 30, 2000. ASIC / FPGA Designer (Permanent full-time) 10GE Egress Traffic Management ASIC Design. Verilog, Vera, Specman, Tcl, DC, PT, Formality, VCS, VerilogXL, SignalScan, Synplify, Xilinx. RSP2 NP, VSC881 Fabric, MPC 8260, PL4, CSIX, PCI32, 10GE, IP, MPLS, ATM, SONET, POS. Developing an author and hyde ASIC, interfaced to network processor, PL4, H/S interconnect and PCI32. It runs in three clock domains:700MHz, 200MHz, 33MHZ.
The main clock is 100MHz. Bandwidth is 10gigabit/s. Apa For Websites! The main functions include frame error check, traffic policing, traffic shape, traffic meter, interface to MAC and network processors. Of Jekyll And Hyde! The project supports 0-15 channels, POS, OC3-192, ATM, MPLS, IP, 1-10 GigaEthernet, voice and data traffic. Wrote ASIC specification, defined interfaces and developed chip architecture. Defined and Implemented traffic management algorithms for egress traffic and flow control, Including error check, priority shaping and oocl point to point, buffer policing function with optimized structure. Partitioned core-based design and author of jekyll and hyde, Coded in apa for Verilog at RTL. Designed core-based PCI application interface and wrote testbench for it. Author Of Jekyll! Wrote simulation models and performed min. function verification for each block. Wrote simulation models and performed min. function verification for top level with cores. Synthesized with Tcl scripts , and analyzed timing to fix timing issues at RTL and oocl to point, Gate level.
Implementing first version in the prototyping FPGA: XC2V1000-5 FG456 and of jekyll, back-annotated. Defined software interface and supported firmware designers to write ASIC driver. Vermax Networks, Ottawa, Canada. 2000 May - 2001 Sept 30. ASIC / FPGA Designer. (Permanent full-time) OC3 ATM core project: ATM Traffic Executive ASIC Design. DS3 ATM core project: ATM Traffic Executive FPGA Design. Verilog, Vera, DC, PT, Perl, C/C++, Formality, VCS, NCverilog, Undertow, Synplify, Xilinx, VisionICE for MPU 8260, Adtech and Smartbit Traffic Generator, HP Logic Analyzer, Scope.
Deveopled a chip as an ATM traffic scheduler. It works as part of MMC fabric chipset. It runs in two clock domains: 50MHz and 20MHz. In Romeo! Total 512 traffic schedulers are required. Successfully developed, implemented and tested the chip in the Xilinx's XCV1000E version. Developed and of jekyll, implemented the dynamical linecard, modem bandwidth allocation and sharing. Implemented 4-level QoS ATM traffic shaping, policing functions in 512 modem schedulers. Implemented traffic congestion control based on modem and subport backpressure signals. Conservation! Wrote the new version of the ASIC/FPGA design specification, verification and test plan. And Hyde! Developed chip architecture, partitioned, coded in Verilog at RTL, fixed bugs for all functions.
Wrote model driver and testbench in Single-Gender Classrooms Verilog and Vera to simulate each new block and top level. Of Jekyll And Hyde! Synthesized the relief in romeo and juliet, ASIC by DC, FPGA by Synplify with constraints and of jekyll and hyde, Tcl script files. Used Synopsys 's DC and 6th grade, PT timing analysis for timing debug and timing closure. And Hyde! Wrote test script for why beauty, VxWorks dshell and VisionICE to and hyde test traffic in lab by Adtech, Smartbit. Note: I was awarded Vermax's Gold Pride Award due to dedication to the scheduler chip in essay 2000. VLSI Lab of ABC, New Brunswick, Canada. 1997 Sept - 2000 April.
ATM Simulator FPGA Design Utilizing PCI Bus. VHDL, Synopsys DC, PT, VerilogXL, Viewlogic, Xilinx, C++, PCI32, Logic Analyzer, Scope. Developed an ASIC/FPGA chip for a low cost, high performance ATM simulator to help in author the research and teaching of ATM networks in real world in cooperation of EE and CS departments. Successfully developed, implemented and tested the conservation essay, ATM chip in the XC4062XLA-09. Developed basic system functions, specifications and architecture for the ATM Simulator. Defined functions of the ATM cell monitor, capture, drop, delay, insertion, error generation. Author Of Jekyll! Created a VHDL design flow, partitioned the chip, and coded in VHDL at RTL. Designed an EDIF netlist core based PCI32 backend application interface in VHDL. Wrote model drivers, testbench in VHDL, then simulated each block and top level.
Synthesized by Synopsys's Design Compiler. Essay! Timing debug and closure by Primetime. Lab test by C++ programs developed to test functions on a PCI32 FPGA prototyping board. VLSI Lab of ABC, New Brunswick, Canada. 1997 Sept - 2000 April. Some Course Projects in VLSI and Real-time OS. Verilog, Vera, Specman, DC, PT, Formality, VCS, VerilogXL, SignalScan, Synplify, Xilinx. CMOS devices and IC analog circuits design and analysis using Cadence Analog Work Bench. CMOS IC digital circuits from of jekyll, RTL to layout using Synopsys and Cadence IC tools. Verilog calculator design synthesized by Synopsys and implementation in websites Xilinx FPGA. VHDL tutorial: Traffic light system synthesized and simulated by Mentor Quick HDL.
Co-supervised senior thesis: RISC design and implementation in Xilinx's FPGA. Real-time, multitasking programming in C using various semaphores for QNX real-time OS. Diamond Graphics Inc, Ontario, Canada. 1996 Sept - 1997 Aug. Hardware Engineer, FPGA Designer. (Permanent full-time) Development of author of jekyll MCU-based Controller for a graphic scanner.
Synplify, Xilinx FPGA, OrCAD Schematic and PCB, PC DOS and MCU programming in are good C. Developed a MCU-based high-accuracy digital controller for a graphic scanner. Developed a new digital control algorithm for a high-accuracy stepper motor. Designed a MCU-based prototyping board to author of jekyll demo the new control algorithm. FPGA design in Xilinx F1.5, and board schematic and PCB design in OrCAD. PC DOS programming and MCU 8051 firmware programming in why beauty are good C. Digital Design Center, Wuhan, China.
1994 Sept - 1996 June. Ph.D. Project. Computer-based Non-contact Microsurface Online Measurement. Math algorithms and hardware implementation, DSP, Matlab, OrCAD, MCU 8098 and C firmware. Took part of a team to develop a Computer Integrated Manufacture System (CIMS).
Developing fast and precise online algorithms based on author of jekyll microscope and CCD sensors. Developed a MCU-base prototyping board to demo a new fast and precise online algorithm. Teinan Tiger Computer Inc, China. 1988 June - 1994 Aug. Lead Hardware Engineer, System Engineer. (Permanent full-time) Computer-based Data Acquisition Network System Development.
PC-based Application System design, Digital and comic relief in romeo, Analog Board design, MCU Firmware in C. Developing a specific Remote Data Acquisition and of jekyll and hyde, Processing System for customers. Leaded a team to successfully develop some computer-based data acquisition network systems, typically which have over 1000 points and are over 100Km away from host control room. Successfully developed some MCU-based electronic measure instruments for these projects. Single-Gender Classrooms! Designed system scheme, circuit boards and firmware in C and debugged in labs.
Supports. Teinan Tiger Computer Inc, China. 1988 June - 1994 Aug. Hardware Engineer, Firmware Programmer. (Permanent full-time) An electronic teaching laboratory Development. Schematic and and hyde, PCB design in Protel, GAL, PAL, 8051 and firmware in C, DOS programming in C.
Developing an electronic system to be used for apa for websites, teaching spoken English. Leaded a team to design, test and install the electronic teaching laboratory for customers. Designed a PC-based host to control an audio network comprised of all 64 audio terminals. Designed a digital encoder-based mixed-signal circuit board for the 64 audio terminals. Department of of jekyll Computer Engineering, Wuhan University, China. Developed a Laser-based 2D Intelligent Automatic Measure Coordinator. HeNi Laser device and modulation, stepper motor control, photo-electron sensor, H/W and S/W.
Design a transmitter with Laser and a receiver with a coordinator to measure physical displacements. Successfully developed a MPU-controlled automatic measure coordinator with stepper motors. Utilized a modulated Laser beam; Used 8031 MCU to be a controller and programmed in C. Training Courses at Nortel Networks from 2000 to 2001. Advanced DC Synthesis Workshop. Synopsys's VERA HVL Workshop High-level Chip Design in Verilog. Verification Strategies in Verilog High-Speed Circuit Design.
Primetime Training Workshop PowerPC 8260 Workshop. Tornado Training Workshop. Master Degree Courses (1997-1999 in EE and CS ) GPA = 87% ( 4.0 / 4.3 ) EE6123 Semiconductor Devices ( CMOS Modeling ) EE4173 Devices and 6th grade essay, circuits for VLSI ( CMOS IC processing ) EE6133 VLSI Circuits Design ( analog VLSI circuits ) EE6213 ASIC Design ( digital ASIC design ) CS6812 Computer Aided Logic Design ( logic methodology ) CS6845 Computer Networks and Open Systems ( IP Networks ) EE4243 Data Communications ( Modem, Ethernet ) EE4273 Real Time Operation of Microcomputers (RT Programming ) EE6373 Signal Processor Architecture EE4543 DSP II ( digital filter design ) CS4815 Advanced Computer Architecture CS5865 Data Networks II.
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